diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index ac43dfc74..8652d7862 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -137,7 +137,9 @@ class XilinxVivadoToolchain: for filename, language, library in platform.sources: filename_tcl = "{" + filename + "}" if (language == "systemverilog"): - tcl.append("read_verilog -sv " + filename_tcl) + tcl.append("read_verilog -v " + filename_tcl) + tcl.append("set_property file_type SystemVerilog [get_files {}]" + .format(filename_tcl)) elif (language == "verilog"): tcl.append("read_verilog " + filename_tcl) elif (language == "vhdl"): diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 9f3d4fb7c..296938f4a 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -120,7 +120,7 @@ class BlackParrotRV64(CPU): def add_sources(platform, variant="standard"): vdir = get_data_mod("cpu", "blackparrot").data_location bp_litex_dir = os.path.join(vdir,"bp_litex") - simulation = 1 + simulation = 0 if (simulation == 1): filename= os.path.join(bp_litex_dir,"flist.verilator") else: @@ -144,7 +144,7 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1]+ line[s2:-1] - platform.add_source(vdir) #this line might be changed + platform.add_source(vdir, "systemverilog") #this line might be changed elif (temp[0] == '/'): assert("No support for absolute path for now") diff --git a/litex_setup.py b/litex_setup.py index 287cc076a..bc4a98c79 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -48,6 +48,7 @@ repos = [ ("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)), ("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True)), ("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)), ] repos = OrderedDict(repos)