From 9036050364c78dbefaa30fdd426545b4900b30cb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 30 Nov 2021 15:32:48 +0100 Subject: [PATCH 1/2] cores/gpio/GPIOTristate: Allow passing platform resource with subsignals directly. --- litex/soc/cores/gpio.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index b92057666..64cf1c2e1 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -73,8 +73,8 @@ class GPIOInOut(Module): class GPIOTristate(_GPIOIRQ, Module, AutoCSR): def __init__(self, pads, with_irq=False): - assert isinstance(pads, Signal) or isinstance(pads, Record) - nbits = len(pads) if isinstance(pads, Signal) else len(pads.o) + internal = not (hasattr(pads, "o") and hasattr(pads, "oe") and hasattr(pads, "i")) + nbits = len(pads) if internal else len(pads.o) self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.") self._in = CSRStatus(nbits, description="GPIO Input(s) Status.") @@ -82,7 +82,10 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR): # # # - if isinstance(pads, Signal): + # Internal Tristate. + if internal: + if isinstance(pads, Record): + pads = pads.raw_bits() # Proper inout IOs. for i in range(nbits): t = TSTriple() @@ -90,6 +93,8 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR): self.comb += t.oe.eq(self._oe.storage[i]) self.comb += t.o.eq(self._out.storage[i]) self.specials += MultiReg(t.i, self._in.status[i]) + + # External Tristate. else: # Tristate inout IOs (For external tristate IO chips or simulation). for i in range(nbits): From 16a43e983ed32e140bd19ab3263bc1161c610460 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 30 Nov 2021 15:48:34 +0100 Subject: [PATCH 2/2] cores/gpio/GPIOTristate: Use Record.flatten() instead of Record.raw_bits(). Fix verilog syntax error. --- litex/soc/cores/gpio.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index 64cf1c2e1..113935770 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -85,7 +85,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR): # Internal Tristate. if internal: if isinstance(pads, Record): - pads = pads.raw_bits() + pads = pads.flatten() # Proper inout IOs. for i in range(nbits): t = TSTriple()