From 5eeb999694b288196b17cfef49d979d3fe45c6d7 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Sat, 18 May 2024 16:59:27 +0200 Subject: [PATCH] update vexii --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index cd6108132..e4cfbc38f 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -132,7 +132,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "8a239d10", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "4d2ff4b2", args.update_repo) VexiiRiscv.jtag_tap = args.with_jtag_tap VexiiRiscv.jtag_instruction = args.with_jtag_instruction