From 9374196974274aa1ad957afef25578572d2ce81b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 11:03:16 +0100 Subject: [PATCH 1/3] soc/cores/uart: allows 64bits in Stream2Wishbone --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index d6ab38a30..a929a0a8a 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -311,7 +311,7 @@ class Stream2Wishbone(LiteXModule): # # # assert data_width in [8, 16, 32] - assert address_width in [8, 16, 32] + assert address_width in [8, 16, 32, 64] cmd = Signal(8, reset_less=True) incr = Signal() From f06ef5205a8cb727b827d3c84d1e0ff8f5f81478 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 11:13:40 +0100 Subject: [PATCH 2/3] soc/cores/uart: adding address_width (default 32bits) to UARTBone constructor --- litex/soc/cores/uart.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index a929a0a8a..f4e0fec28 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -431,17 +431,17 @@ class Stream2Wishbone(LiteXModule): class UARTBone(Stream2Wishbone): - def __init__(self, phy, clk_freq, cd="sys"): + def __init__(self, phy, clk_freq, cd="sys", address_width=32): if cd == "sys": self.phy = phy - Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq) + Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq, address_width=address_width) else: self.phy = ClockDomainsRenamer(cd)(phy) self.tx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=cd) self.rx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from=cd, cd_to="sys") self.comb += self.phy.source.connect(self.rx_cdc.sink) self.comb += self.tx_cdc.source.connect(self.phy.sink) - Stream2Wishbone.__init__(self, clk_freq=clk_freq) + Stream2Wishbone.__init__(self, clk_freq=clk_freq, address_width=address_width) self.comb += self.rx_cdc.source.connect(self.sink) self.comb += self.source.connect(self.tx_cdc.sink) From 321254cc389bf458695e0fe934a37e55d7342a3f Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 30 Oct 2023 11:14:30 +0100 Subject: [PATCH 3/3] soc/integration/soc: pass bus.address_width to UARTBone constructor --- litex/soc/integration/soc.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 3fd236338..7e5588658 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1481,7 +1481,11 @@ class LiteXSoC(SoC): clk_freq = self.sys_clk_freq self.check_if_exists(name) uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate) - uartbone = uart.UARTBone(phy=uartbone_phy, clk_freq=clk_freq, cd=cd) + uartbone = uart.UARTBone( + phy = uartbone_phy, + clk_freq = clk_freq, + cd = cd, + addr_width = self.bus.address_width) self.add_module(name=f"{name}_phy", module=uartbone_phy) self.add_module(name=name, module=uartbone) self.bus.add_master(name=name, master=uartbone.wishbone)