From 60124be293f5e8b3c2741d243f67366fd4a9acb6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Apr 2015 22:52:19 +0200 Subject: [PATCH] adapt LiteSATA to new SoC --- misoclib/mem/litesata/example_designs/make.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py index c8f67b3d2..80452cdfc 100755 --- a/misoclib/mem/litesata/example_designs/make.py +++ b/misoclib/mem/litesata/example_designs/make.py @@ -69,6 +69,8 @@ if __name__ == "__main__": top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() # decode actions action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"] @@ -124,7 +126,7 @@ BIST: {} subprocess.call(["rm", "-rf", "build/*"]) if actions["build-csr-csv"]: - csr_csv = cpuif.get_csr_csv(soc.get_csr_regions()) + csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) if actions["build-core"]: