From 603a4ef51e4c256469280c6a33911d1e00d5fb46 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 10 Apr 2015 11:42:25 +0800 Subject: [PATCH] liteeth: adapt to new ModuleTransformer --- misoclib/com/liteeth/mac/frontend/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/com/liteeth/mac/frontend/wishbone.py b/misoclib/com/liteeth/mac/frontend/wishbone.py index 00747f92c..46e009366 100644 --- a/misoclib/com/liteeth/mac/frontend/wishbone.py +++ b/misoclib/com/liteeth/mac/frontend/wishbone.py @@ -23,7 +23,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR): wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True) for n in range(nrxslots)] # TODO: FullMemoryWE should move to Mibuild - wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram.reader.mems[n], read_only=False)) + wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False)) for n in range(ntxslots)] wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs