From 60e2cdfe7972ba2884d8fa6611d1eaf2a60bedba Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 11 Mar 2013 20:05:30 +0100 Subject: [PATCH] get_registers --> get_registers_glue since it's conflicting with new Migen register automatic detection --- examples/de0_nano/top.py | 2 +- miscope/trigger.py | 22 ++++++++++------------ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 51163aa7d..9181df1dc 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -103,7 +103,7 @@ class SoC: self.miLa0.trigger.bank.bus, self.miLa0.recorder.bank.bus, self.miLa1.trigger.bank.bus, - self.miLa1.recorder.bank.bus + self.miLa1.recorder.bank.bus ]) self.clk50 = Signal() diff --git a/miscope/trigger.py b/miscope/trigger.py index 55ace7c1a..80599b6fb 100644 --- a/miscope/trigger.py +++ b/miscope/trigger.py @@ -39,14 +39,14 @@ class Term: self.reg_p = RegParams("term_reg", 0, width, 2) self.reg = None - def get_registers(self): + def get_registers_glue(self): comb = [self.t.eq(self.reg.field.r[0*self.width:1*self.width])] comb += [self.m.eq(self.reg.field.r[1*self.width:2*self.width])] return comb def get_fragment(self): comb = [self.o.eq((self.m & self.i) == self.t)] - comb += self.get_registers() + comb += self.get_registers_glue() return Fragment(comb) # @@ -75,14 +75,14 @@ class RangeDetector: self.high = Signal(width) self.o = Signal() - def get_registers(self): + def get_registers_glue(self): comb = [self.low.eq(self.reg.field.r[0*self.width:1*self.width])] comb += [self.low.eq(self.reg.field.r[1*self.width:2*self.width])] return comb def get_fragment(self): comb = [self.o.eq((self.i >= self.low) & (self.i <= self.high))] - comb += self.get_registers() + comb += self.get_registers_glue() return Fragment(comb) # # Driver @@ -118,7 +118,7 @@ class EdgeDetector: self.bo = Signal() self.o = Signal() - def get_registers(self): + def get_registers_glue(self): comb = [] i = 0 if "R" in self.mode: @@ -158,7 +158,7 @@ class EdgeDetector: comb += [self.o.eq(self.ro | self.fo | self.bo)] # Registers - comb += self.get_registers() + comb += self.get_registers_glue() return Fragment(comb, sync) @@ -197,8 +197,6 @@ class Sum: self.width = width self.interface = None - - self.i = Signal(self.width) self._o = Signal() self.o = Signal() @@ -214,7 +212,7 @@ class Sum: self._lut_port = self._mem.get_port() self._prog_port = self._mem.get_port(write_capable=True) - def get_registers(self): + def get_registers_glue(self): comb = [ self.prog_adr.eq(self.reg.field.r[0:16]), self.prog_dat.eq(self.reg.field.r[16]), @@ -233,7 +231,7 @@ class Sum: self.o.eq(self._o) ] - comb += self.get_registers() + comb += self.get_registers_glue() return Fragment(comb, specials={self._mem}) # @@ -267,12 +265,12 @@ class Trigger: # generate ports csr registers fields for port in self.ports: rf = RegisterField(port.reg_p.name, port.reg_p.size, reset=0, - access_bus=WRITE_ONLY, access_dev=READ_ONLY) + access_bus=WRITE_ONLY, access_dev=READ_ONLY) setattr(self, port.reg_p.name, rf) # generate sum csr registers fields self.sum_reg = RegisterField(self.sum.reg_p.name, self.sum.reg_p.size, reset=0, - access_bus=WRITE_ONLY, access_dev=READ_ONLY) + access_bus=WRITE_ONLY, access_dev=READ_ONLY) # generate registers self.regs = list_regs(self.__dict__)