diff --git a/milkymist/asmicon/__init__.py b/milkymist/asmicon/__init__.py index 828ccd642..5ea25c118 100644 --- a/milkymist/asmicon/__init__.py +++ b/milkymist/asmicon/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import dfi, asmibus from milkymist.asmicon.refresher import * diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py index 0e296fb0a..361631de6 100644 --- a/milkymist/asmicon/bankmachine.py +++ b/milkymist/asmicon/bankmachine.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus.asmibus import * from migen.genlib.roundrobin import * from migen.genlib.fsm import FSM diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py index ae254418c..9793c5516 100644 --- a/milkymist/asmicon/multiplexer.py +++ b/milkymist/asmicon/multiplexer.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.roundrobin import * from migen.genlib.misc import optree from migen.genlib.fsm import FSM @@ -26,7 +25,7 @@ class _CommandChooser(Module): self.want_reads = Signal() self.want_writes = Signal() # NB: cas_n/ras_n/we_n are 1 when stb is inactive - self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba), tagbits) + self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba), tagbits) ### @@ -83,7 +82,7 @@ class _Steerer(Module): class _Datapath(Module): def __init__(self, timing_settings, command, dfi, hub): - tagbits = len(hub.tag_call) + tagbits = flen(hub.tag_call) rd_valid = Signal() rd_tag = Signal(tagbits) @@ -136,7 +135,7 @@ class Multiplexer(Module): # Command choosing requests = [bm.cmd for bm in bank_machines] - tagbits = len(hub.tag_call) + tagbits = flen(hub.tag_call) choose_cmd = _CommandChooser(requests, tagbits) choose_req = _CommandChooser(requests, tagbits) self.comb += [ diff --git a/milkymist/asmicon/refresher.py b/milkymist/asmicon/refresher.py index 3ad0334b3..cda70433e 100644 --- a/milkymist/asmicon/refresher.py +++ b/milkymist/asmicon/refresher.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.misc import timeline from migen.genlib.fsm import FSM diff --git a/milkymist/asmiprobe/__init__.py b/milkymist/asmiprobe/__init__.py index c449357fc..ca9f9851a 100644 --- a/milkymist/asmiprobe/__init__.py +++ b/milkymist/asmiprobe/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * class ASMIprobe(Module): diff --git a/milkymist/counteradc/__init__.py b/milkymist/counteradc/__init__.py index b785ee080..9df83c352 100644 --- a/milkymist/counteradc/__init__.py +++ b/milkymist/counteradc/__init__.py @@ -1,5 +1,6 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +import collections + +from migen.fhdl.std import * from migen.bank.description import * from migen.genlib.misc import optree from migen.genlib.cdc import MultiReg diff --git a/milkymist/dfii/__init__.py b/milkymist/dfii/__init__.py index 2db5d56ef..22a5bcd5e 100644 --- a/milkymist/dfii/__init__.py +++ b/milkymist/dfii/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import dfi from migen.bank.description import * @@ -7,10 +6,10 @@ class PhaseInjector(Module, AutoCSR): def __init__(self, phase): self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden self._command_issue = CSR() - self._address = CSRStorage(len(phase.address)) - self._baddress = CSRStorage(len(phase.bank)) - self._wrdata = CSRStorage(len(phase.wrdata)) - self._rddata = CSRStatus(len(phase.rddata)) + self._address = CSRStorage(flen(phase.address)) + self._baddress = CSRStorage(flen(phase.bank)) + self._wrdata = CSRStorage(flen(phase.wrdata)) + self._rddata = CSRStatus(flen(phase.rddata)) ### diff --git a/milkymist/dvisampler/__init__.py b/milkymist/dvisampler/__init__.py index 6819fb183..5b74f53a9 100644 --- a/milkymist/dvisampler/__init__.py +++ b/milkymist/dvisampler/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import AutoCSR from milkymist.dvisampler.edid import EDID diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py index d402ce085..a1fa46ebf 100644 --- a/milkymist/dvisampler/analysis.py +++ b/milkymist/dvisampler/analysis.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.genlib.fifo import AsyncFIFO from migen.genlib.record import Record diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py index 63a5b1ccb..3a50b3d38 100644 --- a/milkymist/dvisampler/chansync.py +++ b/milkymist/dvisampler/chansync.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.genlib.fifo import _inc from migen.genlib.record import Record, layout_len diff --git a/milkymist/dvisampler/charsync.py b/milkymist/dvisampler/charsync.py index bb55ea4ba..92e38e9f5 100644 --- a/milkymist/dvisampler/charsync.py +++ b/milkymist/dvisampler/charsync.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.genlib.misc import optree from migen.bank.description import * diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py index be7f833f1..e718e4b1c 100644 --- a/milkymist/dvisampler/clocking.py +++ b/milkymist/dvisampler/clocking.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module -from migen.fhdl.specials import Instance +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.bank.description import * diff --git a/milkymist/dvisampler/datacapture.py b/milkymist/dvisampler/datacapture.py index fa0caab16..8cb060c7e 100644 --- a/milkymist/dvisampler/datacapture.py +++ b/milkymist/dvisampler/datacapture.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module -from migen.fhdl.specials import Instance +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg, PulseSynchronizer from migen.bank.description import * diff --git a/milkymist/dvisampler/debug.py b/milkymist/dvisampler/debug.py index 3eb778617..21d937ed8 100644 --- a/milkymist/dvisampler/debug.py +++ b/milkymist/dvisampler/debug.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.fifo import AsyncFIFO from migen.genlib.record import layout_len from migen.bank.description import AutoCSR diff --git a/milkymist/dvisampler/decoding.py b/milkymist/dvisampler/decoding.py index d051a86c5..034f45435 100644 --- a/milkymist/dvisampler/decoding.py +++ b/milkymist/dvisampler/decoding.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.record import Record from milkymist.dvisampler.common import control_tokens, channel_layout diff --git a/milkymist/dvisampler/dma.py b/milkymist/dvisampler/dma.py index 1eddc4221..1a361b17f 100644 --- a/milkymist/dvisampler/dma.py +++ b/milkymist/dvisampler/dma.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.fsm import FSM from migen.bank.description import * from migen.bank.eventmanager import * diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py index f42b9dfdf..c2726a471 100644 --- a/milkymist/dvisampler/edid.py +++ b/milkymist/dvisampler/edid.py @@ -1,6 +1,5 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory, Tristate -from migen.fhdl.module import Module +from migen.fhdl.std import * +from migen.fhdl.specials import Tristate from migen.genlib.cdc import MultiReg from migen.genlib.fsm import FSM from migen.genlib.misc import chooser diff --git a/milkymist/dvisampler/wer.py b/milkymist/dvisampler/wer.py index 5e9a23800..89d89a0ec 100644 --- a/milkymist/dvisampler/wer.py +++ b/milkymist/dvisampler/wer.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * from migen.genlib.misc import optree from migen.genlib.cdc import PulseSynchronizer diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py index 4161d6fbc..58ebfbc91 100644 --- a/milkymist/framebuffer/__init__.py +++ b/milkymist/framebuffer/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.actor import * from migen.flow.network import * from migen.bank.description import CSRStorage, AutoCSR diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py index 7fa5c9bd9..79ed0ad46 100644 --- a/milkymist/framebuffer/lib.py +++ b/milkymist/framebuffer/lib.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.record import Record from migen.genlib.fifo import AsyncFIFO from migen.flow.actor import * diff --git a/milkymist/gpio/__init__.py b/milkymist/gpio/__init__.py index f2ac9abe4..d02332eca 100644 --- a/milkymist/gpio/__init__.py +++ b/milkymist/gpio/__init__.py @@ -1,16 +1,15 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.bank.description import * class GPIOIn(Module, AutoCSR): def __init__(self, signal): - self._r_in = CSRStatus(len(signal)) + self._r_in = CSRStatus(flen(signal)) self.specials += MultiReg(signal, self._r_in.status) class GPIOOut(Module, AutoCSR): def __init__(self, signal): - self._r_out = CSRStorage(len(signal)) + self._r_out = CSRStorage(flen(signal)) self.comb += signal.eq(self._r_out.storage) class Blinker(Module): diff --git a/milkymist/identifier/__init__.py b/milkymist/identifier/__init__.py index 3fc27422f..ca792fd1b 100644 --- a/milkymist/identifier/__init__.py +++ b/milkymist/identifier/__init__.py @@ -1,7 +1,6 @@ import re -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * def encode_version(version): diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py index 8792b0108..35cf81cad 100644 --- a/milkymist/lm32/__init__.py +++ b/milkymist/lm32/__init__.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import wishbone class LM32(Module): diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py index 9e1511f6c..e163c1bfe 100644 --- a/milkymist/m1crg/__init__.py +++ b/milkymist/m1crg/__init__.py @@ -1,8 +1,6 @@ from fractions import Fraction -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * class M1CRG(Module, AutoCSR): diff --git a/milkymist/minimac3/__init__.py b/milkymist/minimac3/__init__.py index 308b0045f..37efdd490 100644 --- a/milkymist/minimac3/__init__.py +++ b/milkymist/minimac3/__init__.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * from migen.bank.eventmanager import * from migen.bus import wishbone diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py index 705d2ae61..241d6acf2 100644 --- a/milkymist/norflash/__init__.py +++ b/milkymist/norflash/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.misc import timeline @@ -9,7 +8,7 @@ class NorFlash(Module): ### - adr_width = len(pads.adr) + 1 + adr_width = flen(pads.adr) + 1 self.comb += [pads.oe_n.eq(0), pads.we_n.eq(1), pads.ce_n.eq(0)] self.sync += timeline(self.bus.cyc & self.bus.stb, [ diff --git a/milkymist/s6ddrphy/__init__.py b/milkymist/s6ddrphy/__init__.py index 6f7b470d9..bd684ce90 100644 --- a/milkymist/s6ddrphy/__init__.py +++ b/milkymist/s6ddrphy/__init__.py @@ -1,20 +1,18 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import dfi class S6DDRPHY(Module): def __init__(self, pads): - self.dfi = dfi.Interface(len(pads.a), len(pads.ba), 2*len(pads.dq), 2) + self.dfi = dfi.Interface(flen(pads.a), flen(pads.ba), 2*flen(pads.dq), 2) self.clk4x_wr_strb = Signal() self.clk4x_rd_strb = Signal() ### inst_items = [ - Instance.Parameter("NUM_AD", len(pads.a)), - Instance.Parameter("NUM_BA", len(pads.ba)), - Instance.Parameter("NUM_D", 2*len(pads.dq)), + Instance.Parameter("NUM_AD", flen(pads.a)), + Instance.Parameter("NUM_BA", flen(pads.ba)), + Instance.Parameter("NUM_D", 2*flen(pads.dq)), Instance.Input("sys_clk", ClockSignal()), Instance.Input("clk2x_270", ClockSignal("sys2x_270")), diff --git a/milkymist/timer/__init__.py b/milkymist/timer/__init__.py index 81c36f1cc..3d1ab705c 100644 --- a/milkymist/timer/__init__.py +++ b/milkymist/timer/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * from migen.bank.eventmanager import * diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py index 2fcb19d5f..25530d626 100644 --- a/milkymist/uart/__init__.py +++ b/milkymist/uart/__init__.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.bank.description import * from migen.bank.eventmanager import * diff --git a/tb/asmicon/asmicon.py b/tb/asmicon/asmicon.py index 6daafd91f..399a18b38 100644 --- a/tb/asmicon/asmicon.py +++ b/tb/asmicon/asmicon.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.bus.asmibus import * from migen.sim.generic import Simulator, TopLevel diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py index 10e56e8a3..e5efe0f43 100644 --- a/tb/asmicon/asmicon_wb.py +++ b/tb/asmicon/asmicon_wb.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.bus import wishbone, wishbone2asmi, asmibus from migen.sim.generic import Simulator, TopLevel diff --git a/tb/asmicon/bankmachine.py b/tb/asmicon/bankmachine.py index 0221fbd67..fd495d6ec 100644 --- a/tb/asmicon/bankmachine.py +++ b/tb/asmicon/bankmachine.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.bus.asmibus import * from migen.sim.generic import Simulator, TopLevel diff --git a/tb/asmicon/common.py b/tb/asmicon/common.py index a9a4b303b..b41956c3f 100644 --- a/tb/asmicon/common.py +++ b/tb/asmicon/common.py @@ -1,7 +1,7 @@ from fractions import Fraction from math import ceil -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.sim.generic import Proxy from milkymist import asmicon diff --git a/tb/asmicon/refresher.py b/tb/asmicon/refresher.py index a044fcb51..79b9b1895 100644 --- a/tb/asmicon/refresher.py +++ b/tb/asmicon/refresher.py @@ -1,6 +1,6 @@ from random import Random -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.sim.generic import Simulator, TopLevel from milkymist.asmicon.refresher import * diff --git a/tb/asmicon/selector.py b/tb/asmicon/selector.py index 3b99774bd..ee987814e 100644 --- a/tb/asmicon/selector.py +++ b/tb/asmicon/selector.py @@ -1,6 +1,6 @@ from random import Random -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.bus.asmibus import * from migen.sim.generic import Simulator, TopLevel diff --git a/tb/dvisampler/chansync.py b/tb/dvisampler/chansync.py index 549ffe0e1..cc38e07e2 100644 --- a/tb/dvisampler/chansync.py +++ b/tb/dvisampler/chansync.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.sim.generic import * from milkymist.dvisampler.chansync import ChanSync diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py index 76b1f7ac1..bddde1be3 100644 --- a/tb/framebuffer/framebuffer.py +++ b/tb/framebuffer/framebuffer.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.bus import asmibus from migen.sim.generic import Simulator diff --git a/top.py b/top.py index 3ea99a6f9..1ab79e12d 100644 --- a/top.py +++ b/top.py @@ -2,8 +2,7 @@ from fractions import Fraction from math import ceil from operator import itemgetter -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi from migen.bank import csrgen