From 6170c904597bc5210e829fea0caf2ba76c1befb4 Mon Sep 17 00:00:00 2001 From: Richard Tucker Date: Thu, 19 Oct 2023 12:21:47 +1100 Subject: [PATCH] soc/cores/spi_mmap: adjust CSR mapping to better suit drivers Currently the TX_RX_ENGINE CSR register lives below the slot registers which are dynamic in length (based on how many slots (chip selects) are configured in the gateware). Move the TX_RX_ENGINE CSR to above the SLOT configuration registers so TX_RX_ENGINE never moves. This makes for an easier and cleaner driver. --- litex/soc/cores/spi/spi_mmap.py | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py index acb9300ed..663078c1f 100644 --- a/litex/soc/cores/spi/spi_mmap.py +++ b/litex/soc/cores/spi/spi_mmap.py @@ -239,6 +239,7 @@ class SPICtrl(LiteXModule): default_slot_bitorder = SPI_SLOT_BITORDER_MSB_FIRST, default_slot_loopback = 0b1, default_slot_divider = 2, + default_enable = 0b1, ): self.nslots = nslots self.slot_controls = [] @@ -302,6 +303,13 @@ class SPICtrl(LiteXModule): self.ev.rx.trigger.eq(self.rx_status.fields.level > self.rx_control.fields.threshold), ] + self.engine = CSRStorage(fields=[ + CSRField("enable", size=1, offset=0, values=[ + ("``0b0``", "SPI Engine Disabled."), + ("``0b1``", "SPI Engine Enabled."), + ], reset=default_enable), + ]) + # Create Slots Control/Status registers. for slot in range(nslots): control = CSRStorage(name=f"slot_control{slot}", fields=[ @@ -487,7 +495,7 @@ class SPIRXMMAP(LiteXModule): # SPI Engine --------------------------------------------------------------------------------------- class SPIEngine(LiteXModule): - def __init__(self, pads, ctrl, data_width, sys_clk_freq, default_enable=0b1): + def __init__(self, pads, ctrl, data_width, sys_clk_freq): self.sink = sink = stream.Endpoint(spi_layout( data_width = data_width, be_width = data_width//8, @@ -499,13 +507,6 @@ class SPIEngine(LiteXModule): cs_width = len(pads.cs_n) )) - self.control = CSRStorage(fields=[ - CSRField("enable", size=1, offset=0, values=[ - ("``0b0``", "SPI Engine Disabled."), - ("``0b1``", "SPI Engine Enabled."), - ], reset=default_enable), - ]) - # # # # SPI Master. @@ -544,7 +545,7 @@ class SPIEngine(LiteXModule): ] # SPI CS. (Use Manual CS to allow back-to-back Xfers). - self.comb += If(self.control.fields.enable & sink.valid, + self.comb += If(ctrl.engine.fields.enable & sink.valid, spi.cs.eq(sink.cs) ) @@ -555,7 +556,7 @@ class SPIEngine(LiteXModule): # Control-Path. self.fsm = fsm = FSM(reset_state="START") fsm.act("START", - If(self.control.fields.enable & sink.valid, + If(ctrl.engine.fields.enable & sink.valid, spi.start.eq(1), NextState("XFER") )