diff --git a/litex/gen/fhdl/memory.py b/litex/gen/fhdl/memory.py
index 19602db17..ad2863be2 100644
--- a/litex/gen/fhdl/memory.py
+++ b/litex/gen/fhdl/memory.py
@@ -12,14 +12,15 @@ from migen.fhdl.tools import *
 from migen.fhdl.verilog import _printexpr as verilog_printexpr
 from migen.fhdl.specials import *
 
-def memory_emit_verilog(memory, ns, add_data_file):
+
+def memory_emit_verilog(memory, namespace, add_data_file):
     # Helpers.
     # --------
     def gn(e):
         if isinstance(e, Memory):
-            return ns.get_name(e)
+            return namespace.get_name(e)
         else:
-            return verilog_printexpr(ns, e)[0]
+            return verilog_printexpr(namespace, e)[0]
 
     # Parameters.
     # -----------
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 517727e15..d97940ed4 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -490,7 +490,7 @@ def _print_synchronous_logic(f, ns):
 #                                      SPECIALS                                                    #
 # ------------------------------------------------------------------------------------------------ #
 
-def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
+def _print_specials(name, overrides, specials, namespace, add_data_file, attr_translate):
     r = ""
     for special in sorted(specials, key=lambda x: x.duid):
         if hasattr(special, "attr"):
@@ -500,9 +500,9 @@ def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
         # Replace Migen Memory's emit_verilog with LiteX's implementation.
         if isinstance(special, Memory):
             from litex.gen.fhdl.memory import memory_emit_verilog
-            pr = memory_emit_verilog(special, ns, add_data_file)
+            pr = memory_emit_verilog(special, namespace, add_data_file)
         else:
-            pr = call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
+            pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file)
         if pr is None:
             raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
         r += pr
@@ -610,8 +610,14 @@ def convert(f, ios=set(), name="top", platform=None,
 
     # Specials
     verilog += _print_separator("Specialized Logic")
-    verilog += _print_specials(special_overrides, f.specials - lowered_specials,
-        ns, r.add_data_file, attr_translate)
+    verilog += _print_specials(
+        name           = name,
+        overrides      =special_overrides,
+        specials       = f.specials - lowered_specials,
+        namespace      = ns,
+        add_data_file  = r.add_data_file,
+        attr_translate = attr_translate
+    )
 
     # Module End.
     verilog += "endmodule\n"