From 62cf95c5da3f4d9813913ceeb0c6ecd2e67c449a Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 10 Apr 2024 12:21:47 +0200 Subject: [PATCH] cpu/vexii add git --- litex/soc/cores/cpu/vexiiriscv/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 1d86cbb95..6cd7db20f 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -129,8 +129,8 @@ class VexiiRiscv(CPU): def args_read(args): print(args) - # if args.update_repo != "no": - # NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "main", "ec3ee4dc" if args.update_repo=="recommended" else None) + if args.update_repo != "no": + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "main", "af662e86" if args.update_repo=="recommended" else None)