From fb5130fc1fbebe88d68f04e96b6b2819b180eea5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 7 Feb 2013 22:07:30 +0100 Subject: [PATCH 01/83] Initial version --- mibuild/__init__.py | 0 mibuild/crg.py | 18 +++ mibuild/generic_platform.py | 209 ++++++++++++++++++++++++++++++++++ mibuild/platforms/__init__.py | 0 mibuild/platforms/rhino.py | 131 +++++++++++++++++++++ mibuild/tools.py | 12 ++ mibuild/xilinx_ise.py | 122 ++++++++++++++++++++ 7 files changed, 492 insertions(+) create mode 100644 mibuild/__init__.py create mode 100644 mibuild/crg.py create mode 100644 mibuild/generic_platform.py create mode 100644 mibuild/platforms/__init__.py create mode 100644 mibuild/platforms/rhino.py create mode 100644 mibuild/tools.py create mode 100644 mibuild/xilinx_ise.py diff --git a/mibuild/__init__.py b/mibuild/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/mibuild/crg.py b/mibuild/crg.py new file mode 100644 index 000000000..0d4dcfbb5 --- /dev/null +++ b/mibuild/crg.py @@ -0,0 +1,18 @@ +from migen.fhdl.structure import * + +class CRG: + def get_clock_domains(self): + r = dict() + for k, v in self.__dict__.items(): + if isinstance(v, ClockDomain): + r[v.name] = v + return r + + def get_fragment(self): + return Fragment() + +class SimpleCRG(CRG): + def __init__(self, platform, clk_name, rst_name): + self.cd = ClockDomain("sys") + platform.request(clk_name, None, self.cd.clk) + platform.request(rst_name, None, self.cd.rst) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py new file mode 100644 index 000000000..387755288 --- /dev/null +++ b/mibuild/generic_platform.py @@ -0,0 +1,209 @@ +from copy import copy + +from migen.fhdl.structure import * +from migen.corelogic.record import Record +from migen.fhdl import verilog + +class ConstraintError(Exception): + pass + +class Pins: + def __init__(self, *identifiers): + self.identifiers = identifiers + +class IOStandard: + def __init__(self, name): + self.name = name + +class Drive: + def __init__(self, strength): + self.strength = strength + +class Misc: + def __init__(self, misc): + self.misc = misc + +class Subsignal: + def __init__(self, name, *constraints): + self.name = name + self.constraints = list(constraints) + +def _lookup(description, name, number): + for resource in description: + if resource[0] == name and (number is None or resource[1] == number): + return resource + return ConstraintError("Resource not found") + +def _resource_type(resource): + t = None + for element in resource[2:]: + if isinstance(element, Pins): + assert(t is None) + t = len(element.identifiers) + elif isinstance(element, Subsignal): + if t is None: + t = [] + assert(isinstance(t, list)) + n_bits = None + for c in element.constraints: + if isinstance(c, Pins): + assert(n_bits is None) + n_bits = len(c.identifiers) + t.append((element.name, n_bits)) + return t + +def _match(description, requests): + available = list(description) + matched = [] + + # 1. Match requests for a specific number + for request in requests: + if request[1] is not None: + resource = _lookup(available, request[0], request[1]) + available.remove(resource) + matched.append((resource, request[2])) + + # 2. Match requests for no specific number + for request in requests: + if request[1] is None: + resource = _lookup(available, request[0], request[1]) + available.remove(resource) + matched.append((resource, request[2])) + + return matched + +def _separate_pins(constraints): + pins = None + others = [] + for c in constraints: + if isinstance(c, Pins): + assert(pins is None) + pins = c.identifiers + else: + others.append(c) + return pins, others + +class ConstraintManager: + def __init__(self, description): + self.description = description + self.requests = [] + self.platform_commands = [] + + def request(self, name, number=None, obj=None): + r = _lookup(self.description, name, number) + t = _resource_type(r) + + # If obj is None, then create it. + # If it already exists, do some sanity checking. + if obj is None: + if isinstance(t, int): + obj = Signal(t, name_override=r[0]) + else: + obj = Record(t) + else: + if isinstance(t, int): + assert(isinstance(obj, Signal) and obj.nbits == t) + else: + for e in t: + sig = getattr(obj, e[0]) + assert(isinstance(sig, Signal) and sig.nbits == e[1]) + + # Register the request + self.requests.append((name, number, obj)) + + return obj + + def add_platform_command(self, command, **signals): + self.platform_commands.append((command, signals)) + + def get_io_signals(self): + s = set() + for req in self.requests: + obj = req[2] + if isinstance(obj, Signal): + s.add(obj) + else: + for k in obj.__dict__: + p = getattr(obj, k) + if isinstance(p, Signal): + s.add(p) + return s + + def get_sig_constraints(self): + r = [] + matched = _match(self.description, self.requests) + for resource, obj in matched: + name = resource[0] + number = resource[1] + has_subsignals = False + top_constraints = [] + for element in resource[2:]: + if isinstance(element, Subsignal): + has_subsignals = True + else: + top_constraints.append(element) + if has_subsignals: + for element in resource[2:]: + if isinstance(element, Subsignal): + sig = getattr(obj, element.name) + pins, others = _separate_pins(top_constraints + element.constraints) + r.append((sig, pins, others, (name, number, element.name))) + else: + pins, others = _separate_pins(top_constraints) + r.append((obj, pins, others, (name, number, None))) + return r + + def get_platform_commands(self): + return self.platform_commands + + def save(self): + return copy(self.requests), copy(self.platform_commands) + + def restore(self, backup): + self.request, self.platform_commands = backup + +class GenericPlatform: + def __init__(self, device, io, default_crg_factory=None): + self.device = device + self.constraint_manager = ConstraintManager(io) + self.default_crg_factory = default_crg_factory + + def request(self, *args, **kwargs): + return self.constraint_manager.request(*args, **kwargs) + + def add_platform_command(self, *args, **kwargs): + return self.constraint_manager.add_platform_command(*args, **kwargs) + + def get_verilog(self, fragment, clock_domains=None): + # We may create a temporary clock/reset generator that would request pins. + # Save the constraint manager state so that such pin requests disappear + # at the end of this function. + backup = self.constraint_manager.save() + try: + # if none exists, create a default clock domain and drive it + if clock_domains is None: + if self.default_crg_factory is None: + raise NotImplementedError("No clock/reset generator defined by either platform or user") + crg = self.default_crg_factory(self) + frag = fragment + crg.get_fragment() + clock_domains = crg.get_clock_domains() + else: + frag = fragment + # generate Verilog + src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), + clock_domains=clock_domains, return_ns=True) + # resolve signal names in constraints + sc = self.constraint_manager.get_sig_constraints() + named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] + # resolve signal names in platform commands + pc = self.constraint_manager.get_platform_commands() + named_pc = [] + for template, args in pc: + name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items()) + named_pc.append(template.format(**name_dict)) + finally: + self.constraint_manager.restore(backup) + return src, named_sc, named_pc + + def build(self, fragment, clock_domains=None): + raise NotImplementedError("GenericPlatform.build must be overloaded") diff --git a/mibuild/platforms/__init__.py b/mibuild/platforms/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py new file mode 100644 index 000000000..9c562ba6c --- /dev/null +++ b/mibuild/platforms/rhino.py @@ -0,0 +1,131 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS + +_io = [ + ("user_led", 0, Pins("Y3")), + ("user_led", 1, Pins("Y1")), + ("user_led", 2, Pins("W2")), + ("user_led", 3, Pins("W1")), + ("user_led", 4, Pins("V3")), + ("user_led", 5, Pins("V1")), + ("user_led", 6, Pins("U2")), + ("user_led", 7, Pins("U1")), + + ("clk100", 0, + Subsignal("p", Pins("B14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("n", Pins("A14"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) + ), + + ("gpio", 0, Pins("R8")), + + ("gpmc", 0, + Subsignal("clk", Pins("R26")), + Subsignal("a", Pins("N17", "N18", "L23", "L24", "N19", "N20", "N21", "N22", "P17", "P19")), + Subsignal("d", Pins("N23", "N24", "R18", "R19", "P21", "P22", "R20", "R21", "P24", "P26", "R23", "R24", "T22", "T23", "U23", "R25")), + Subsignal("we_n", Pins("W26")), + Subsignal("oe_n", Pins("AA25")), + Subsignal("ale_n", Pins("AA26")), + IOStandard("LVCMOS33")), + # Warning: CS are numbered 1-7 on ARM side and 0-6 on FPGA side. + # Numbers here are given on the FPGA side. + ("gpmc_ce_n", 0, Pins("V23"), IOStandard("LVCMOS33")), # nCS0 + ("gpmc_ce_n", 1, Pins("U25"), IOStandard("LVCMOS33")), # nCS1 + ("gpmc_ce_n", 2, Pins("W25"), IOStandard("LVCMOS33")), # nCS6 + ("gpmc_dmareq_n", 0, Pins("T24"), IOStandard("LVCMOS33")), # nCS2 + ("gpmc_dmareq_n", 1, Pins("T26"), IOStandard("LVCMOS33")), # nCS3 + ("gpmc_dmareq_n", 2, Pins("V24"), IOStandard("LVCMOS33")), # nCS4 + ("gpmc_dmareq_n", 3, Pins("V26"), IOStandard("LVCMOS33")), # nCS5 + + # FMC150 + ("fmc150_ctrl", 0, + Subsignal("spi_sclk", Pins("AE5")), + Subsignal("spi_data", Pins("AF5")), + + Subsignal("adc_sdo", Pins("U13")), + Subsignal("adc_en_n", Pins("AA15")), + Subsignal("adc_reset", Pins("V13")), + + Subsignal("cdce_sdo", Pins("AA8")), + Subsignal("cdce_en_n", Pins("Y9")), + Subsignal("cdce_reset_n", Pins("AB7")), + Subsignal("cdce_pd_n", Pins("AC6")), + Subsignal("cdce_pll_status", Pins("W7")), + Subsignal("cdce_ref_en", Pins("W8")), + + Subsignal("dac_sdo", Pins("W9")), + Subsignal("dac_en_n", Pins("W10")), + + Subsignal("mon_sdo", Pins("AC5")), + Subsignal("mon_en_n", Pins("AD6")), + Subsignal("mon_reset_n", Pins("AF6")), + Subsignal("mon_int_n", Pins("AD5")), + + Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33")) + ), + ("ti_dac", 0, # DAC3283 + Subsignal("dat_p", Pins("AA10", "AA9", "V11", "Y11", "W14", "Y12", "AD14", "AE13"), IOStandard("LVDS_25")), + Subsignal("dat_n", Pins("AB11", "AB9", "V10", "AA11", "Y13", "AA12", "AF14", "AF13"), IOStandard("LVDS_25")), + Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")), + Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")), + Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25")) + ), + ("ti_adc", 0, # ADS62P49 + Subsignal("dat_a_p", Pins("AB14", "Y21", "W20", "AB22", "V18", "W17", "AA21")), + Subsignal("dat_a_n", Pins("AC14", "AA22", "Y20", "AC22", "W19", "W18", "AB21")), + Subsignal("dat_b_p", Pins("Y17", "U15", "AA19", "W16", "AA18", "Y15", "V14")), + Subsignal("dat_b_n", Pins("AA17", "V16", "AB19", "Y16", "AB17", "AA16", "V15")), + IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") + ), + ("fmc150_clocks", 0, + Subsignal("dac_clk_p", Pins("V12"), IOStandard("LVDS_25")), + Subsignal("dac_clk_n", Pins("W12"), IOStandard("LVDS_25")), + Subsignal("adc_clk_p", Pins("AE15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("adc_clk_n", Pins("AF15"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("clk_to_fpga", Pins("W24"), IOStandard("LVCMOS25")) + ), + + ("fmc150_ext_trigger", 0, Pins("U26")), + + # Vermeer radar testbed + # TX path + ("pe43602", 0, + Subsignal("d", Pins("H8")), + Subsignal("clk", Pins("B3")), + Subsignal("le", Pins("F7")), + IOStandard("LVCMOS33") + ), + ("rfmd2081", 0, + Subsignal("enx", Pins("E5")), + Subsignal("sclk", Pins("G6")), + Subsignal("sdata", Pins("F5")), + Subsignal("sdatao", Pins("E6")), + IOStandard("LVCMOS33") + ), + # RX path + ("lmh6521", 0, + Subsignal("scsb", Pins("C5")), + Subsignal("sclk", Pins("G10")), + Subsignal("sdi", Pins("D5")), + Subsignal("sdo", Pins("F9")), + IOStandard("LVCMOS33") + ), + ("lmh6521", 1, + Subsignal("scsb", Pins("E10")), + Subsignal("sclk", Pins("A4")), + Subsignal("sdi", Pins("B4")), + Subsignal("sdo", Pins("H10")), + IOStandard("LVCMOS33") + ), + ("rffc5071", 0, + Subsignal("enx", Pins("A2")), + Subsignal("sclk", Pins("G9")), + Subsignal("sdata", Pins("H9")), + Subsignal("sdatao", Pins("A3")), + IOStandard("LVCMOS33") + ) +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io, + lambda p: CRG_DS(p, "clk100", "gpio", 10.0)) diff --git a/mibuild/tools.py b/mibuild/tools.py new file mode 100644 index 000000000..565312a26 --- /dev/null +++ b/mibuild/tools.py @@ -0,0 +1,12 @@ +import os + +def mkdir_noerror(d): + try: + os.mkdir(d) + except OSError: + pass + +def write_to_file(filename, contents): + f = open(filename, "w") + f.write(contents) + f.close() diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py new file mode 100644 index 000000000..ce82b383c --- /dev/null +++ b/mibuild/xilinx_ise.py @@ -0,0 +1,122 @@ +import os, struct, subprocess +from decimal import Decimal + +from migen.fhdl.structure import * + +from mibuild.generic_platform import * +from mibuild.crg import CRG, SimpleCRG +from mibuild import tools + +def _add_period_constraint(platform, clk, period): + platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk"; +TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) + +class CRG_SE(SimpleCRG): + def __init__(self, platform, clk_name, rst_name, period): + SimpleCRG.__init__(self, platform, clk_name, rst_name) + _add_period_constraint(platform, self.cd.clk, period) + +class CRG_DS(CRG): + def __init__(self, platform, clk_name, rst_name, period): + self.cd = ClockDomain("sys") + self._clk = platform.request(clk_name) + platform.request(rst_name, None, self.cd.rst) + _add_period_constraint(platform, self._clk.p, period) + + def get_fragment(self): + ibufg = Instance("IBUFGDS", + Instance.Input("I", self._clk.p), + Instance.Input("IB", self._clk.n), + Instance.Output("O", self.cd.clk) + ) + return Fragment(instances=[ibufg]) + +def _format_constraint(c): + if isinstance(c, Pins): + return "LOC=" + c.identifiers[0] + elif isinstance(c, IOStandard): + return "IOSTANDARD=" + c.name + elif isinstance(c, Drive): + return "DRIVE=" + str(c.strength) + elif isinstance(c, Misc): + return c.misc + +def _format_ucf(signame, pin, others, resname): + fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)] + fmt_r = resname[0] + ":" + str(resname[1]) + if resname[2] is not None: + fmt_r += "." + resname[2] + return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n" + +def _build_ucf(named_sc, named_pc): + r = "" + for sig, pins, others, resname in named_sc: + if len(pins) > 1: + for i, p in enumerate(pins): + r += _format_ucf(sig + "(" + str(i) + ")", p, others, resname) + else: + r += _format_ucf(sig, pins[0], others, resname) + if named_pc: + r += "\n" + "\n\n".join(named_pc) + return r + +def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path): + tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) + + prj_contents = "" + for s in sources: + prj_contents += s["type"] + " work " + s["path"] + "\n" + tools.write_to_file(build_name + ".prj", prj_contents) + + xst_contents = """run +-ifn %s.prj +-top top +-ifmt MIXED +-opt_mode SPEED +-reduce_control_sets auto +-ofn %s.ngc +-p %s""" % (build_name, build_name, device) + tools.write_to_file(build_name + ".xst", xst_contents) + + def is_valid_version(v): + try: + Decimal(v) + return os.path.isdir(os.path.join(xilinx_install_path, v)) + except: + return False + vers = [ver for ver in os.listdir(xilinx_install_path) if is_valid_version(ver)] + tools_version = max(vers) + bits = struct.calcsize("P")*8 + xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (xilinx_install_path, tools_version, bits) + + build_script_contents = """# Autogenerated by mibuild + +set -e + +source {xilinx_settings_file} +xst -ifn {build_name}.xst +ngdbuild -uc {build_name}.ucf {build_name}.ngc +map -ol high -w {build_name}.ngd +par -ol high -w {build_name}.ncd {build_name}-routed.ncd +bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit +""".format(build_name=build_name, xilinx_settings_file=xilinx_settings_file) + build_script_file = "build_" + build_name + ".sh" + tools.write_to_file(build_script_file, build_script_contents) + + r = subprocess.call(["bash", build_script_file]) + if r != 0: + raise OSError("Subprocess failed") + +class XilinxISEPlatform(GenericPlatform): + def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", + xilinx_install_path="/opt/Xilinx"): + tools.mkdir_noerror(build_dir) + os.chdir(build_dir) + + v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains) + v_file = build_name + ".v" + tools.write_to_file(v_file, v_src) + sources = [{"type": "verilog", "path": v_file}] + _build(self.device, sources, named_sc, named_pc, build_name, xilinx_install_path) + + os.chdir("..") From 25882c6c8382b8ab82e2422fb6b918b4435165ff Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 7 Feb 2013 22:38:33 +0100 Subject: [PATCH 02/83] platforms: ROACH (incomplete) --- mibuild/platforms/roach.py | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 mibuild/platforms/roach.py diff --git a/mibuild/platforms/roach.py b/mibuild/platforms/roach.py new file mode 100644 index 000000000..de46fcc78 --- /dev/null +++ b/mibuild/platforms/roach.py @@ -0,0 +1,33 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform + +_io = [ + ("epb", 0, + Subsignal("cs_n", Pins("K13")), + Subsignal("r_w_n", Pins("AF20")), + Subsignal("be_n", Pins("AF14", "AF18")), + Subsignal("oe_n", Pins("AF21")), + Subsignal("addr", Pins("AE23", "AE22", "AG18", "AG12", "AG15", "AG23", "AF19", "AE12", "AG16", "AF13", "AG20", "AF23", + "AH17", "AH15", "L20", "J22", "H22", "L15", "L16", "K22", "K21", "K16", "J15")), + Subsignal("addr_gp", Pins("L21", "G22", "K23", "K14", "L14", "J12")), + Subsignal("data", Pins("AF15", "AE16", "AE21", "AD20", "AF16", "AE17", "AE19", "AD19", "AG22", "AH22", "AH12", "AG13", + "AH20", "AH19", "AH14", "AH13")), + Subsignal("rdy", Pins("K12")), + IOStandard("LVCMOS33") + ), + ("roach_clocks", 0, + Subsignal("epb_clk", Pins("AH18"), IOStandard("LVCMOS33")), + Subsignal("sys_clk_n", Pins("H13")), + Subsignal("sys_clk_p", Pins("J14")), + Subsignal("aux0_clk_p", Pins("G15")), + Subsignal("aux0_clk_n", Pins("G16")), + Subsignal("aux1_clk_p", Pins("H14")), + Subsignal("aux1_clk_n", Pins("H15")), + Subsignal("dly_clk_n", Pins("J17")), + Subsignal("dly_clk_p", Pins("J16")), + ), +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io) From 78f8ec1a53daf2b09dcf662621e066f7d4ab16b7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 17:42:35 +0100 Subject: [PATCH 03/83] platforms: add M1 --- mibuild/platforms/m1.py | 91 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 mibuild/platforms/m1.py diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py new file mode 100644 index 000000000..d343738e1 --- /dev/null +++ b/mibuild/platforms/m1.py @@ -0,0 +1,91 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE + +_io = [ + ("user_led", 0, Pins("B16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + ("user_led", 1, Pins("A16"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + ("user_btn", 0, Pins("AB4"), IOStandard("LVCMOS33")), + ("user_btn", 1, Pins("AA4"), IOStandard("LVCMOS33")), + ("user_btn", 2, Pins("AB5"), IOStandard("LVCMOS33")), + + ("clk50", 0, Pins("AB11"), IOStandard("LVCMOS33")), + + # When executing softcore code in-place from the flash, we want + # the flash reset to be released before the system reset. + ("norflash_reset", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), + ("norflash", 0, + Subsignal("adr", Pins("L22", "L20", "K22", "K21", "J19", "H20", "F22", + "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20", + "G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19")), + Subsignal("d", Pins("AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7", + "AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"), Misc("PULLDOWN")), + Subsignal("oe_n", Pins("M22")), + Subsignal("we_n", Pins("N20")), + Subsignal("ce_n", Pins("M21")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8) + ), + + ("serial", 0, + Subsignal("tx", IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + + ("ddram_clock", 0, + Subsignal("p", Pins("M3")), + Subsignal("n", Pins("L4")), + IOStandard("SSTL2_I") + ), + ("ddram", 0, + Subsignal("a", Pins("B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5", + "G6", "C1", "C3", "D1", "D2")), + Subsignal("ba", Pins("A2", "E6")), + Subsignal("cs_n", Pins("F7")), + Subsignal("cke", Pins("G7")), + Subsignal("ras_n", Pins("E5")), + Subsignal("cas_n", Pins("C4")), + Subsignal("we_n", Pins("D3")), + Subsignal("dq", Pins("Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3", + "U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4", + "M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1")), + Subsignal("dm", Pins("E1", "E3", "F3", "G4")), + Subsignal("dqs", Pins("F1", "F2", "H5", "H6")), + IOStandard("SSTL2_I") + ), + + ("eth_clocks", 0, + Subsignal("phy", Pins("M20")), + Subsignal("rx", Pins("H22")), + Subsignal("tx", Pins("H21")), + IOStandard("LVCMOS33") + ), + ("eth", 0, + Subsignal("rst_n", Pins("R22")), + Subsignal("dv", Pins("V21")), + Subsignal("rx_er", Pins("V22")), + Subsignal("rx_data", Pins("U22", "U20", "T22", "T21")), + Subsignal("tx_en", Pins("N19")), + Subsignal("tx_er", Pins("M19")), + Subsignal("tx_data", Pins("M16", "L15", "P19", "P20")), + Subsignal("col", Pins("W20")), + Subsignal("crs", Pins("W22")), + IOStandard("LVCMOS33") + ), + + ("vga_clock", 0, Pins("A11"), IOStandard("LVCMOS33")), + ("vga", 0, + Subsignal("r", Pins("C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9")), + Subsignal("g", Pins("C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10")), + Subsignal("b", Pins("D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14")), + Subsignal("hsync_n", Pins("A14")), + Subsignal("vsync_n", Pins("C15")), + Subsignal("psave_n", Pins("B14")), + IOStandard("LVCMOS33") + ), +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, + lambda p: CRG_SE(p, "clk50", "user_btn", 20.0)) From fef9d0fc78e81a9cbbf6feb55cf1c3ec60b55750 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 17:43:04 +0100 Subject: [PATCH 04/83] generic_platform: fix typo --- mibuild/generic_platform.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 387755288..8e2496414 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -32,7 +32,7 @@ def _lookup(description, name, number): for resource in description: if resource[0] == name and (number is None or resource[1] == number): return resource - return ConstraintError("Resource not found") + raise ConstraintError("Resource not found") def _resource_type(resource): t = None From 9ecfdeccec3aa9a987b52e8bc80e04f7f21aa8d9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 17:44:13 +0100 Subject: [PATCH 05/83] platforms/rhino: add PCA9555 I2C expander --- mibuild/platforms/rhino.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index 9c562ba6c..eadd135c8 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -87,6 +87,12 @@ _io = [ ("fmc150_ext_trigger", 0, Pins("U26")), # Vermeer radar testbed + # Switch controller + ("pca9555", 0, + Subsignal("sda", Pins("C13")), + Subsignal("scl", Pins("G8")), + IOStandard("LVCMOS33") + ), # TX path ("pe43602", 0, Subsignal("d", Pins("H8")), From 32dcfc6d02ec7955bfe196f3c7c077bb5a3516b5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 18:27:46 +0100 Subject: [PATCH 06/83] generic_platform: support name remapping --- mibuild/generic_platform.py | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 8e2496414..bc03cf32a 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -34,7 +34,7 @@ def _lookup(description, name, number): return resource raise ConstraintError("Resource not found") -def _resource_type(resource): +def _resource_type(resource, name_map): t = None for element in resource[2:]: if isinstance(element, Pins): @@ -49,7 +49,7 @@ def _resource_type(resource): if isinstance(c, Pins): assert(n_bits is None) n_bits = len(c.identifiers) - t.append((element.name, n_bits)) + t.append((name_map(element.name), n_bits)) return t def _match(description, requests): @@ -61,14 +61,14 @@ def _match(description, requests): if request[1] is not None: resource = _lookup(available, request[0], request[1]) available.remove(resource) - matched.append((resource, request[2])) + matched.append((resource, request[2], request[3])) # 2. Match requests for no specific number for request in requests: if request[1] is None: resource = _lookup(available, request[0], request[1]) available.remove(resource) - matched.append((resource, request[2])) + matched.append((resource, request[2], request[3])) return matched @@ -89,27 +89,27 @@ class ConstraintManager: self.requests = [] self.platform_commands = [] - def request(self, name, number=None, obj=None): + def request(self, name, number=None, obj=None, name_map=lambda s: s): r = _lookup(self.description, name, number) - t = _resource_type(r) + t = _resource_type(r, name_map) # If obj is None, then create it. # If it already exists, do some sanity checking. if obj is None: if isinstance(t, int): - obj = Signal(t, name_override=r[0]) + obj = Signal(t, name_override=name_map(r[0])) else: obj = Record(t) else: if isinstance(t, int): assert(isinstance(obj, Signal) and obj.nbits == t) else: - for e in t: - sig = getattr(obj, e[0]) - assert(isinstance(sig, Signal) and sig.nbits == e[1]) + for name, nbits in t: + sig = getattr(obj, name) + assert(isinstance(sig, Signal) and sig.nbits == nbits) # Register the request - self.requests.append((name, number, obj)) + self.requests.append((name, number, obj, name_map)) return obj @@ -123,8 +123,7 @@ class ConstraintManager: if isinstance(obj, Signal): s.add(obj) else: - for k in obj.__dict__: - p = getattr(obj, k) + for p in obj.__dict__.values(): if isinstance(p, Signal): s.add(p) return s @@ -132,7 +131,7 @@ class ConstraintManager: def get_sig_constraints(self): r = [] matched = _match(self.description, self.requests) - for resource, obj in matched: + for resource, obj, name_map in matched: name = resource[0] number = resource[1] has_subsignals = False @@ -145,7 +144,7 @@ class ConstraintManager: if has_subsignals: for element in resource[2:]: if isinstance(element, Subsignal): - sig = getattr(obj, element.name) + sig = getattr(obj, name_map(element.name)) pins, others = _separate_pins(top_constraints + element.constraints) r.append((sig, pins, others, (name, number, element.name))) else: From 7b8e8a19f320d6c37e748bc7d7a08bb6ba953e84 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 20:25:20 +0100 Subject: [PATCH 07/83] Support adding Verilog/VHDL files --- mibuild/generic_platform.py | 22 ++++++++++++++++++++++ mibuild/tools.py | 8 ++++++++ mibuild/xilinx_ise.py | 6 +++--- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index bc03cf32a..b78f2a4cd 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -1,9 +1,12 @@ from copy import copy +import os from migen.fhdl.structure import * from migen.corelogic.record import Record from migen.fhdl import verilog +from mibuild import tools + class ConstraintError(Exception): pass @@ -166,6 +169,7 @@ class GenericPlatform: self.device = device self.constraint_manager = ConstraintManager(io) self.default_crg_factory = default_crg_factory + self.sources = [] def request(self, *args, **kwargs): return self.constraint_manager.request(*args, **kwargs) @@ -173,6 +177,24 @@ class GenericPlatform: def add_platform_command(self, *args, **kwargs): return self.constraint_manager.add_platform_command(*args, **kwargs) + def add_source(self, filename, language=None): + if language is None: + language = tools.language_by_filename(filename) + if language is None: + language = "verilog" # default to Verilog + self.sources.append((filename, language)) + + def add_sources(self, path, *filenames, language=None): + for f in filenames: + self.add_source(os.path.join(path, f), language) + + def add_source_dir(self, path): + for root, dirs, files in os.walk(path): + for filename in files: + language = tools.language_by_filename(filename) + if language is not None: + self.add_source(os.path.join(root, filename), language) + def get_verilog(self, fragment, clock_domains=None): # We may create a temporary clock/reset generator that would request pins. # Save the constraint manager state so that such pin requests disappear diff --git a/mibuild/tools.py b/mibuild/tools.py index 565312a26..1c2493e4e 100644 --- a/mibuild/tools.py +++ b/mibuild/tools.py @@ -6,6 +6,14 @@ def mkdir_noerror(d): except OSError: pass +def language_by_filename(name): + extension = name.rsplit(".")[-1] + if extension in ["v", "vh", "vo"]: + return "verilog" + if extension in ["vhd", "vhdl", "vho"]: + return "vhdl" + return None + def write_to_file(filename, contents): f = open(filename, "w") f.write(contents) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index ce82b383c..d13945d43 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -64,8 +64,8 @@ def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path) tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) prj_contents = "" - for s in sources: - prj_contents += s["type"] + " work " + s["path"] + "\n" + for filename, language in sources: + prj_contents += language + " work " + filename + "\n" tools.write_to_file(build_name + ".prj", prj_contents) xst_contents = """run @@ -116,7 +116,7 @@ class XilinxISEPlatform(GenericPlatform): v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) - sources = [{"type": "verilog", "path": v_file}] + sources = self.sources + [(v_file, "verilog")] _build(self.device, sources, named_sc, named_pc, build_name, xilinx_install_path) os.chdir("..") From b092237fa641a4ec338ec79e0766e2d9e8f014ef Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 20:31:45 +0100 Subject: [PATCH 08/83] xilinx_ise: support building files without running ISE --- mibuild/xilinx_ise.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index d13945d43..0d887beca 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -60,7 +60,7 @@ def _build_ucf(named_sc, named_pc): r += "\n" + "\n\n".join(named_pc) return r -def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path): +def _build_files(device, sources, named_sc, named_pc, build_name): tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) prj_contents = "" @@ -78,6 +78,7 @@ def _build(device, sources, named_sc, named_pc, build_name, xilinx_install_path) -p %s""" % (build_name, build_name, device) tools.write_to_file(build_name + ".xst", xst_contents) +def _run_ise(build_name, xilinx_install_path): def is_valid_version(v): try: Decimal(v) @@ -109,7 +110,7 @@ bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit class XilinxISEPlatform(GenericPlatform): def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", - xilinx_install_path="/opt/Xilinx"): + xilinx_install_path="/opt/Xilinx", run=True): tools.mkdir_noerror(build_dir) os.chdir(build_dir) @@ -117,6 +118,8 @@ class XilinxISEPlatform(GenericPlatform): v_file = build_name + ".v" tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")] - _build(self.device, sources, named_sc, named_pc, build_name, xilinx_install_path) + _build_files(self.device, sources, named_sc, named_pc, build_name) + if run: + _run_ise(build_name, xilinx_install_path) os.chdir("..") From f13ad035e14b46b4098d93b621a6362d10472b98 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 8 Feb 2013 22:23:58 +0100 Subject: [PATCH 09/83] Support for command line arguments --- mibuild/generic_platform.py | 14 +++++++++++++- mibuild/xilinx_ise.py | 24 ++++++++++++++++++------ 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index b78f2a4cd..2f8fd4aea 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -1,5 +1,5 @@ from copy import copy -import os +import os, argparse from migen.fhdl.structure import * from migen.corelogic.record import Record @@ -228,3 +228,15 @@ class GenericPlatform: def build(self, fragment, clock_domains=None): raise NotImplementedError("GenericPlatform.build must be overloaded") + + def add_arguments(self, parser): + pass # default: no arguments + + def build_arg_ns(self, ns, *args, **kwargs): + self.build(*args, **kwargs) + + def build_cmdline(self, *args, **kwargs): + parser = argparse.ArgumentParser(description="FPGA bitstream build system") + self.add_arguments(parser) + ns = parser.parse_args() + self.build_arg_ns(ns, *args, **kwargs) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 0d887beca..4012ca40e 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -78,17 +78,17 @@ def _build_files(device, sources, named_sc, named_pc, build_name): -p %s""" % (build_name, build_name, device) tools.write_to_file(build_name + ".xst", xst_contents) -def _run_ise(build_name, xilinx_install_path): +def _run_ise(build_name, ise_path): def is_valid_version(v): try: Decimal(v) - return os.path.isdir(os.path.join(xilinx_install_path, v)) + return os.path.isdir(os.path.join(ise_path, v)) except: return False - vers = [ver for ver in os.listdir(xilinx_install_path) if is_valid_version(ver)] + vers = [ver for ver in os.listdir(ise_path) if is_valid_version(ver)] tools_version = max(vers) bits = struct.calcsize("P")*8 - xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (xilinx_install_path, tools_version, bits) + xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) build_script_contents = """# Autogenerated by mibuild @@ -110,7 +110,7 @@ bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit class XilinxISEPlatform(GenericPlatform): def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", - xilinx_install_path="/opt/Xilinx", run=True): + ise_path="/opt/Xilinx", run=True): tools.mkdir_noerror(build_dir) os.chdir(build_dir) @@ -120,6 +120,18 @@ class XilinxISEPlatform(GenericPlatform): sources = self.sources + [(v_file, "verilog")] _build_files(self.device, sources, named_sc, named_pc, build_name) if run: - _run_ise(build_name, xilinx_install_path) + _run_ise(build_name, ise_path) os.chdir("..") + + def build_arg_ns(self, ns, *args, **kwargs): + for n in ["build_dir", "build_name", "ise_path"]: + kwargs[n] = getattr(ns, n) + kwargs["run"] = not ns.no_run + self.build(*args, **kwargs) + + def add_arguments(self, parser): + parser.add_argument("--build-dir", default="build", help="Set the directory in which to generate files and run ISE") + parser.add_argument("--build-name", default="top", help="Base name for the generated files") + parser.add_argument("--ise-path", default="/opt/Xilinx", help="ISE installation path (without version directory)") + parser.add_argument("--no-run", action="store_true", help="Only generate files, do not run ISE") From 4b78d90aad9d723f0f91c323199eeca3e205df99 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 11 Feb 2013 17:46:03 +0100 Subject: [PATCH 10/83] platforms/m1: add serial pins --- mibuild/platforms/m1.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index d343738e1..e278eb206 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -27,11 +27,10 @@ _io = [ ), ("serial", 0, - Subsignal("tx", IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), - Subsignal("rx", IOStandard("LVCMOS33"), Misc("PULLUP")) + Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")) ), - ("ddram_clock", 0, Subsignal("p", Pins("M3")), Subsignal("n", Pins("L4")), From ce6701c6e48f1f0edc628be608342c6b57f7d478 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 11 Feb 2013 17:46:27 +0100 Subject: [PATCH 11/83] platforms/m1: norflash_reset -> norflash_rst_n --- mibuild/platforms/m1.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index e278eb206..c51b7ea32 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -13,7 +13,7 @@ _io = [ # When executing softcore code in-place from the flash, we want # the flash reset to be released before the system reset. - ("norflash_reset", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), + ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), ("norflash", 0, Subsignal("adr", Pins("L22", "L20", "K22", "K21", "J19", "H20", "F22", "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20", From 709845e61858f2789bd0622362b5012e9ededebe Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 11 Feb 2013 17:54:01 +0100 Subject: [PATCH 12/83] generic_platform: fix request --- mibuild/generic_platform.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 2f8fd4aea..cf2300944 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -35,7 +35,7 @@ def _lookup(description, name, number): for resource in description: if resource[0] == name and (number is None or resource[1] == number): return resource - raise ConstraintError("Resource not found") + raise ConstraintError("Resource not found: " + name + "." + str(number)) def _resource_type(resource, name_map): t = None @@ -107,8 +107,8 @@ class ConstraintManager: if isinstance(t, int): assert(isinstance(obj, Signal) and obj.nbits == t) else: - for name, nbits in t: - sig = getattr(obj, name) + for attr, nbits in t: + sig = getattr(obj, attr) assert(isinstance(sig, Signal) and sig.nbits == nbits) # Register the request From feec035cc89a491249309cd356d9911d8dc68342 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 12 Feb 2013 19:16:00 +0100 Subject: [PATCH 13/83] generic_platform: get absolute path for added sources --- mibuild/generic_platform.py | 1 + 1 file changed, 1 insertion(+) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index cf2300944..f634423d5 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -182,6 +182,7 @@ class GenericPlatform: language = tools.language_by_filename(filename) if language is None: language = "verilog" # default to Verilog + filename = os.path.abspath(filename) self.sources.append((filename, language)) def add_sources(self, path, *filenames, language=None): From ed4d65f2be3b4cf3c5065feb70b6c8f3c2216882 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 13 Feb 2013 23:29:33 +0100 Subject: [PATCH 14/83] generic_platform: fix IO signal set when using existing record objects --- mibuild/generic_platform.py | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index f634423d5..844bcab96 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -35,7 +35,7 @@ def _lookup(description, name, number): for resource in description: if resource[0] == name and (number is None or resource[1] == number): return resource - raise ConstraintError("Resource not found: " + name + "." + str(number)) + raise ConstraintError("Resource not found: " + name + ":" + str(number)) def _resource_type(resource, name_map): t = None @@ -91,6 +91,7 @@ class ConstraintManager: self.description = description self.requests = [] self.platform_commands = [] + self.io_signals = set() def request(self, name, number=None, obj=None, name_map=lambda s: s): r = _lookup(self.description, name, number) @@ -98,18 +99,24 @@ class ConstraintManager: # If obj is None, then create it. # If it already exists, do some sanity checking. + # Update io_signals at the same time. if obj is None: if isinstance(t, int): obj = Signal(t, name_override=name_map(r[0])) + self.io_signals.add(obj) else: obj = Record(t) + for sig in obj.flatten(): + self.io_signals.add(sig) else: if isinstance(t, int): assert(isinstance(obj, Signal) and obj.nbits == t) + self.io_signals.add(obj) else: for attr, nbits in t: sig = getattr(obj, attr) assert(isinstance(sig, Signal) and sig.nbits == nbits) + self.io_signals.add(sig) # Register the request self.requests.append((name, number, obj, name_map)) @@ -120,16 +127,7 @@ class ConstraintManager: self.platform_commands.append((command, signals)) def get_io_signals(self): - s = set() - for req in self.requests: - obj = req[2] - if isinstance(obj, Signal): - s.add(obj) - else: - for p in obj.__dict__.values(): - if isinstance(p, Signal): - s.add(p) - return s + return self.io_signals def get_sig_constraints(self): r = [] @@ -159,10 +157,10 @@ class ConstraintManager: return self.platform_commands def save(self): - return copy(self.requests), copy(self.platform_commands) + return copy(self.requests), copy(self.platform_commands), copy(self.io_signals) def restore(self, backup): - self.request, self.platform_commands = backup + self.request, self.platform_commands, self.io_signals = backup class GenericPlatform: def __init__(self, device, io, default_crg_factory=None): From 38c356671741dddea401c34af42a01fb862a7f3f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 14 Feb 2013 20:02:35 +0100 Subject: [PATCH 15/83] generic_platform: add name --- mibuild/generic_platform.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 844bcab96..09a182147 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -163,10 +163,13 @@ class ConstraintManager: self.request, self.platform_commands, self.io_signals = backup class GenericPlatform: - def __init__(self, device, io, default_crg_factory=None): + def __init__(self, device, io, default_crg_factory=None, name=None): self.device = device self.constraint_manager = ConstraintManager(io) self.default_crg_factory = default_crg_factory + if name is None: + name = self.__module__.split(".")[-1] + self.name = name self.sources = [] def request(self, *args, **kwargs): From 244cfbc7a21d0db5cd323be87e560d4cab93f45c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Feb 2013 19:56:44 +0100 Subject: [PATCH 16/83] add README, LICENSE and gitignore --- .gitignore | 2 + LICENSE | 676 +++++++++++++++++++++++++++++++++++++++++++++++++++++ README | 26 +++ 3 files changed, 704 insertions(+) create mode 100644 .gitignore create mode 100644 LICENSE create mode 100644 README diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..8d35cb327 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +__pycache__ +*.pyc diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..443254047 --- /dev/null +++ b/LICENSE @@ -0,0 +1,676 @@ + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. + diff --git a/README b/README new file mode 100644 index 000000000..1e04545c2 --- /dev/null +++ b/README @@ -0,0 +1,26 @@ +Mibuild (Milkymist Build system) + a build system and board database for Migen-based FPGA designs + +6-ligne intro: + +from migen.fhdl.structure import * +from mibuild.platforms import m1 +plat = m1.Platform() +led = plat.request("user_led") +f = Fragment([led.eq(counter[25])], [counter.eq(counter + 1)]) +plat.build_cmdline(f) + +Code repository: +https://github.com/milkymist/mibuild +Migen: +https://github.com/milkymist/migen +Experimental version of the Milkymist SoC based on Migen: +https://github.com/milkymist/milkymist-ng + +Mibuild is designed for Python 3. + +Send questions, comments and patches to devel [AT] lists.milkymist.org +Description files for new boards welcome. +We are also on IRC: #milkymist on the Freenode network. + +Mibuild is (c) 2013 Sebastien Bourdeauducq and GPLv3 (see LICENSE file). From 44ae20d3c4e32c62599a4b23373f91f5ddd102f3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 20 Feb 2013 18:27:04 +0100 Subject: [PATCH 17/83] generic_platform: prefix subsignals --- mibuild/generic_platform.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 09a182147..aabd1a07f 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -105,7 +105,7 @@ class ConstraintManager: obj = Signal(t, name_override=name_map(r[0])) self.io_signals.add(obj) else: - obj = Record(t) + obj = Record(t, name=r[0]) for sig in obj.flatten(): self.io_signals.add(sig) else: From 0321513726cce7b2160257544983da7e1d48e741 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 23 Feb 2013 19:37:27 +0100 Subject: [PATCH 18/83] corelogic -> genlib --- mibuild/generic_platform.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index aabd1a07f..6777e7658 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -2,7 +2,7 @@ from copy import copy import os, argparse from migen.fhdl.structure import * -from migen.corelogic.record import Record +from migen.genlib.record import Record from migen.fhdl import verilog from mibuild import tools From ef833422c77c83ee81018ceb7cec30914a733fd3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 23 Feb 2013 19:42:29 +0100 Subject: [PATCH 19/83] generic_platform/get_verilog: pass additional args to verilog.convert --- mibuild/generic_platform.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 6777e7658..ca5d9bd07 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -197,7 +197,7 @@ class GenericPlatform: if language is not None: self.add_source(os.path.join(root, filename), language) - def get_verilog(self, fragment, clock_domains=None): + def get_verilog(self, fragment, clock_domains=None, **kwargs): # We may create a temporary clock/reset generator that would request pins. # Save the constraint manager state so that such pin requests disappear # at the end of this function. @@ -214,7 +214,7 @@ class GenericPlatform: frag = fragment # generate Verilog src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), - clock_domains=clock_domains, return_ns=True) + clock_domains=clock_domains, return_ns=True, **kwargs) # resolve signal names in constraints sc = self.constraint_manager.get_sig_constraints() named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] From 56ae0f0714f2159f34d76d15d4fc4ef1077e708e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 23 Feb 2013 19:43:12 +0100 Subject: [PATCH 20/83] xilinx_ise: disable SRL extraction on synchronizers --- mibuild/xilinx_ise.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 4012ca40e..a35ccf7db 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -2,6 +2,8 @@ import os, struct, subprocess from decimal import Decimal from migen.fhdl.structure import * +from migen.fhdl.specials import SynthesisDirective +from migen.genlib.cdc import * from mibuild.generic_platform import * from mibuild.crg import CRG, SimpleCRG @@ -108,7 +110,23 @@ bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit if r != 0: raise OSError("Subprocess failed") +class XilinxMultiRegImpl(MultiRegImpl): + def get_fragment(self): + disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r) + for r in self.regs) + return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl) + +class XilinxMultiReg: + @staticmethod + def lower(dr): + return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n) + class XilinxISEPlatform(GenericPlatform): + def get_verilog(self, *args, special_overrides=dict(), **kwargs): + so = {MultiReg: XilinxMultiReg} + so.update(special_overrides) + return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) + def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", ise_path="/opt/Xilinx", run=True): tools.mkdir_noerror(build_dir) From d60ab1d2154e2b898f7dec475c7eb8a757d74672 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 24 Feb 2013 12:21:01 +0100 Subject: [PATCH 21/83] Use new 'specials' API --- mibuild/xilinx_ise.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index a35ccf7db..a8d65284c 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -31,7 +31,7 @@ class CRG_DS(CRG): Instance.Input("IB", self._clk.n), Instance.Output("O", self.cd.clk) ) - return Fragment(instances=[ibufg]) + return Fragment(specials={ibufg}) def _format_constraint(c): if isinstance(c, Pins): From 2b902fdcbdc2d316061a5e0e701e3f903a6d2cf6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 24 Feb 2013 15:36:56 +0100 Subject: [PATCH 22/83] xilinx_ise: import Instance --- mibuild/xilinx_ise.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index a8d65284c..5a2f6719a 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -2,7 +2,7 @@ import os, struct, subprocess from decimal import Decimal from migen.fhdl.structure import * -from migen.fhdl.specials import SynthesisDirective +from migen.fhdl.specials import Instance, SynthesisDirective from migen.genlib.cdc import * from mibuild.generic_platform import * From 6a412f796e1986dd31a91dc75c6e8592bedfe854 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 1 Mar 2013 11:29:40 +0100 Subject: [PATCH 23/83] xilinx_ise: add lock cycle to bitgen --- mibuild/xilinx_ise.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 5a2f6719a..04cc7cb01 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -101,7 +101,7 @@ xst -ifn {build_name}.xst ngdbuild -uc {build_name}.ucf {build_name}.ngc map -ol high -w {build_name}.ngd par -ol high -w {build_name}.ncd {build_name}-routed.ncd -bitgen -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit +bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit """.format(build_name=build_name, xilinx_settings_file=xilinx_settings_file) build_script_file = "build_" + build_name + ".sh" tools.write_to_file(build_script_file, build_script_contents) From 4d4d6c1f88cceb5c3e72b44dcd8ad326af2bfee9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 5 Mar 2013 23:03:01 +0100 Subject: [PATCH 24/83] platforms/m1: add video mixer extension board --- mibuild/platforms/m1.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index c51b7ea32..5273441a9 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -82,6 +82,26 @@ _io = [ Subsignal("psave_n", Pins("B14")), IOStandard("LVCMOS33") ), + + # Digital video mixer extension board + ("dvi_in", 0, + Subsignal("clk", Pins("A20")), + Subsignal("data0_n", Pins("A21")), + Subsignal("data1", Pins("B21")), + Subsignal("data2_n", Pins("B22")), + Subsignal("scl", Pins("G16")), + Subsignal("sda", Pins("G17")), + IOStandard("LVCMOS33") + ), + ("dvi_in", 1, + Subsignal("clk", Pins("H17")), + Subsignal("data0_n", Pins("H16")), + Subsignal("data1", Pins("F17")), + Subsignal("data2_n", Pins("F16")), + Subsignal("scl", Pins("J16")), + Subsignal("sda", Pins("K16")), + IOStandard("LVCMOS33") + ) ] class Platform(XilinxISEPlatform): From c06a821452be8b331548641d5adc82df9891d0e8 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 12 Mar 2013 16:14:13 +0100 Subject: [PATCH 25/83] generic_platform: implicit get_fragment --- mibuild/generic_platform.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index ca5d9bd07..89360bc49 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -198,6 +198,8 @@ class GenericPlatform: self.add_source(os.path.join(root, filename), language) def get_verilog(self, fragment, clock_domains=None, **kwargs): + if not isinstance(fragment, Fragment): + fragment = fragment.get_fragment() # We may create a temporary clock/reset generator that would request pins. # Save the constraint manager state so that such pin requests disappear # at the end of this function. From 24910173b7ac82573805f3eb1aa87b2c4b76c4f4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 10:48:43 +0100 Subject: [PATCH 26/83] CRG: use new Module API --- mibuild/crg.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/mibuild/crg.py b/mibuild/crg.py index 0d4dcfbb5..6448ec49c 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -1,6 +1,7 @@ from migen.fhdl.structure import * +from migen.fhdl.module import Module -class CRG: +class CRG(Module): def get_clock_domains(self): r = dict() for k, v in self.__dict__.items(): @@ -8,9 +9,6 @@ class CRG: r[v.name] = v return r - def get_fragment(self): - return Fragment() - class SimpleCRG(CRG): def __init__(self, platform, clk_name, rst_name): self.cd = ClockDomain("sys") From 37d8029848db6badb0b7de79f890abfe3ea01493 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 10:49:18 +0100 Subject: [PATCH 27/83] CRG: support reset inversion --- mibuild/crg.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/mibuild/crg.py b/mibuild/crg.py index 6448ec49c..131b7e627 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -10,7 +10,11 @@ class CRG(Module): return r class SimpleCRG(CRG): - def __init__(self, platform, clk_name, rst_name): + def __init__(self, platform, clk_name, rst_name, rst_invert=False): self.cd = ClockDomain("sys") platform.request(clk_name, None, self.cd.clk) - platform.request(rst_name, None, self.cd.rst) + if rst_invert: + rst_n = platform.request(rst_name) + self.comb += self.cd.rst.eq(~rst_n) + else: + platform.request(rst_name, None, self.cd.rst) From 71c817283677d58da610c57bb21a1510d1847b4e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 11:31:36 +0100 Subject: [PATCH 28/83] xilinx_ise/CRG_SE: reset inversion support --- mibuild/xilinx_ise.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 04cc7cb01..698d0b04f 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -14,8 +14,8 @@ def _add_period_constraint(platform, clk, period): TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) class CRG_SE(SimpleCRG): - def __init__(self, platform, clk_name, rst_name, period): - SimpleCRG.__init__(self, platform, clk_name, rst_name) + def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) _add_period_constraint(platform, self.cd.clk, period) class CRG_DS(CRG): From 86d6f1d01164aa14772d4f011aba575b280af507 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 11:32:12 +0100 Subject: [PATCH 29/83] Added support for Altera Quartus (by Florent Kermarrec) --- mibuild/altera_quartus.py | 97 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 mibuild/altera_quartus.py diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py new file mode 100644 index 000000000..831b18b7c --- /dev/null +++ b/mibuild/altera_quartus.py @@ -0,0 +1,97 @@ +import os, subprocess + +from mibuild.generic_platform import * +from mibuild.crg import SimpleCRG +from mibuild import tools + +def _add_period_constraint(platform, clk, period): + platform.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk) + platform.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk) + +class CRG_SE(SimpleCRG): + def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) + _add_period_constraint(platform, self.cd.clk, period) + +def _format_constraint(c): + if isinstance(c, Pins): + return "set_location_assignment PIN_" + c.identifiers[0] + elif isinstance(c, IOStandard): + return "set_instance_assignment -name IO_STANDARD " + "\"" + c.name + "\"" + elif isinstance(c, Misc): + return c.misc + +def _format_qsf(signame, pin, others, resname): + fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)] + fmt_r = resname[0] + ":" + str(resname[1]) + if resname[2] is not None: + fmt_r += "." + resname[2] + r = "" + for c in fmt_c: + r += c + " -to " + signame + " # " + fmt_r + "\n" + return r + +def _build_qsf(named_sc, named_pc): + r = "" + for sig, pins, others, resname in named_sc: + if len(pins) > 1: + for i, p in enumerate(pins): + r += _format_qsf(sig + "[" + str(i) + "]", p, others, resname) + else: + r += _format_qsf(sig, pins[0], others, resname) + if named_pc: + r += "\n" + "\n\n".join(named_pc) + return r + +def _build_files(device, sources, named_sc, named_pc, build_name): + qsf_contents = "" + for filename, language in sources: + qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n" + + qsf_contents += _build_qsf(named_sc, named_pc) + qsf_contents += "set_global_assignment -name DEVICE " + device + tools.write_to_file(build_name + ".qsf", qsf_contents) + +def _run_quartus(build_name, quartus_path): + build_script_contents = """# Autogenerated by mibuild + +quartus_map {build_name}.qpf +quartus_fit {build_name}.qpf +quartus_asm {build_name}.qpf +quartus_sta {build_name}.qpf + +""".format(build_name=build_name) + build_script_file = "build_" + build_name + ".sh" + tools.write_to_file(build_script_file, build_script_contents) + + r = subprocess.call(["bash", build_script_file]) + if r != 0: + raise OSError("Subprocess failed") + +class AlteraQuartusPlatform(GenericPlatform): + def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", + quartus_path="/opt/Altera", run=True): + tools.mkdir_noerror(build_dir) + os.chdir(build_dir) + + v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains) + v_file = build_name + ".v" + tools.write_to_file(v_file, v_src) + sources = self.sources + [(v_file, "verilog")] + _build_files(self.device, sources, named_sc, named_pc, build_name) + if run: + _run_quartus(build_name, quartus_path) + + os.chdir("..") + + def build_arg_ns(self, ns, *args, **kwargs): + for n in ["build_dir", "build_name", "quartus_path"]: + kwargs[n] = getattr(ns, n) + kwargs["run"] = not ns.no_run + self.build(*args, **kwargs) + + def add_arguments(self, parser): + parser.add_argument("--build-dir", default="build", help="Set the directory in which to generate files and run Quartus") + parser.add_argument("--build-name", default="top", help="Base name for the generated files") + parser.add_argument("--quartus-path", default="/opt/Altera", help="Quartus installation path (without version directory)") + parser.add_argument("--no-run", action="store_true", help="Only generate files, do not run Quartus") From f9e07b92a4461a23a918ac3da911eba93db5eaa9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 11:41:38 +0100 Subject: [PATCH 30/83] Added platform file for DE0 Nano (by Florent Kermarrec) --- mibuild/platforms/de0nano.py | 99 ++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 mibuild/platforms/de0nano.py diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py new file mode 100644 index 000000000..05f629f10 --- /dev/null +++ b/mibuild/platforms/de0nano.py @@ -0,0 +1,99 @@ +from mibuild.generic_platform import * +from mibuild.altera_quartus import AlteraQuartusPlatform, CRG_SE + +_io = [ + ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), + + ("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")), + ("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")), + ("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")), + ("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")), + ("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")), + ("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")), + ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), + ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), + + ("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), + + ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), + ("sw", 1, Pins("T9"), IOStandard("3.3-V LVTTL")), + ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), + ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")), + + ("serial", 0, + Subsignal("tx", Pins("D3"), IOStandard("3.3-V LVTTL")), + Subsignal("rx", Pins("C3"), IOStandard("3.3-V LVTTL")) + ), + + ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins("P2", "N5", "N6", "M8", "P8", "T7", "N8", "T6", + "R1", "P1", "N2", "N1", "L4")), + Subsignal("ba", Pins("M7", "M6")), + Subsignal("cs_n", Pins("P6")), + Subsignal("cke", Pins("L7")), + Subsignal("ras_n", Pins("L2")), + Subsignal("cas_n", Pins("L1")), + Subsignal("we_n", Pins("C2")), + Subsignal("dq", Pins("G2", "G1", "L8", "K5", "K2", "J2", "J1", "R7", + "T4", "T2", "T3", "R3", "R5", "P3", "N3", "K1")), + Subsignal("dqm", Pins("R6","T5")), + IOStandard("3.3-V LVTTL") + ), + + ("epcs", 0, + Subsignal("data0", Pins("H2")), + Subsignal("dclk", Pins("H1")), + Subsignal("ncs0", Pins("D2")), + Subsignal("asd0", Pins("C1")), + IOStandard("3.3-V LVTTL") + ), + + ("i2c", 0, + Subsignal("sclk", Pins("F2")), + Subsignal("sdat", Pins("F1")), + IOStandard("3.3-V LVTTL") + ), + + ("g_sensor", 0, + Subsignal("cs_n", Pins("G5")), + Subsignal("int", Pins("M2")), + IOStandard("3.3-V LVTTL") + ), + + ("adc", 0, + Subsignal("cs_n", Pins("A10")), + Subsignal("saddr", Pins("B10")), + Subsignal("sclk", Pins("B14")), + Subsignal("sdat", Pins("A9")), + IOStandard("3.3-V LVTTL") + ), + + ("gpio_0", 0, + Pins("D3", "C3", "A2", "A3", "B3", "B4", "A4", "B5", + "A5", "D5", "B6", "A6", "B7", "D6", "A7", "C6", + "C8", "E6", "E7", "D8", "E8", "F8", "F9", "E9", + "C9", "D9", "E11", "E10", "C11", "B11", "A12", "D11", + "D12", "B12"), + IOStandard("3.3-V LVTTL") + ), + ("gpio_1", 0, + Pins("F13", "T15", "T14", "T13", "R13", "T12", "R12", "T11", + "T10", "R11", "P11", "R10", "N12", "P9", "N9", "N11", + "L16", "K16", "R16", "L15", "P15", "P16", "R14", "N16", + "N15", "P14", "L14", "N14", "M10", "L13", "J16", "K15", + "J13", "J14"), + IOStandard("3.3-V LVTTL") + ), + ("gpio_2", 0, + Pins("A14", "B16", "C14", "C16", "C15", "D16", "D15", "D14", + "F15", "F16", "F14", "G16", "G15"), + IOStandard("3.3-V LVTTL") + ), +] + +class Platform(AlteraQuartusPlatform): + def __init__(self): + AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io, + lambda p: CRG_SE(p, "clk50", "key", 20.0, True)) From 001beadb971f6666258ea1cf8e4cc857a85d3705 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 12:37:25 +0100 Subject: [PATCH 31/83] altera_quartus, de0nano: add copyright notices --- mibuild/altera_quartus.py | 3 +++ mibuild/platforms/de0nano.py | 3 +++ 2 files changed, 6 insertions(+) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 831b18b7c..c73d2474e 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -1,3 +1,6 @@ +# This file is Copyright (c) 2013 Florent Kermarrec +# License: GPLv3 + import os, subprocess from mibuild.generic_platform import * diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index 05f629f10..496591aca 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -1,3 +1,6 @@ +# This file is Copyright (c) 2013 Florent Kermarrec +# License: GPLv3 + from mibuild.generic_platform import * from mibuild.altera_quartus import AlteraQuartusPlatform, CRG_SE From 6feb6e60b065aa28b06b6b22325e3426cf7a9e1a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 18:46:11 +0100 Subject: [PATCH 32/83] New clock_domain API --- mibuild/altera_quartus.py | 4 ++-- mibuild/crg.py | 18 +++++------------- mibuild/generic_platform.py | 10 ++++------ mibuild/xilinx_ise.py | 24 +++++++++++++----------- 4 files changed, 24 insertions(+), 32 deletions(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index c73d2474e..f1d366dfa 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -72,12 +72,12 @@ quartus_sta {build_name}.qpf raise OSError("Subprocess failed") class AlteraQuartusPlatform(GenericPlatform): - def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", + def build(self, fragment, build_dir="build", build_name="top", quartus_path="/opt/Altera", run=True): tools.mkdir_noerror(build_dir) os.chdir(build_dir) - v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains) + v_src, named_sc, named_pc = self.get_verilog(fragment) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")] diff --git a/mibuild/crg.py b/mibuild/crg.py index 131b7e627..5d8510dd7 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -1,20 +1,12 @@ from migen.fhdl.structure import * from migen.fhdl.module import Module -class CRG(Module): - def get_clock_domains(self): - r = dict() - for k, v in self.__dict__.items(): - if isinstance(v, ClockDomain): - r[v.name] = v - return r - -class SimpleCRG(CRG): +class SimpleCRG(Module): def __init__(self, platform, clk_name, rst_name, rst_invert=False): - self.cd = ClockDomain("sys") - platform.request(clk_name, None, self.cd.clk) + self.clock_domains.cd_sys = ClockDomain() + platform.request(clk_name, None, self.cd_sys.clk) if rst_invert: rst_n = platform.request(rst_name) - self.comb += self.cd.rst.eq(~rst_n) + self.comb += self.cd_sys.rst.eq(~rst_n) else: - platform.request(rst_name, None, self.cd.rst) + platform.request(rst_name, None, self.cd_sys.rst) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 89360bc49..d3fe50b22 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -197,7 +197,7 @@ class GenericPlatform: if language is not None: self.add_source(os.path.join(root, filename), language) - def get_verilog(self, fragment, clock_domains=None, **kwargs): + def get_verilog(self, fragment, **kwargs): if not isinstance(fragment, Fragment): fragment = fragment.get_fragment() # We may create a temporary clock/reset generator that would request pins. @@ -206,17 +206,15 @@ class GenericPlatform: backup = self.constraint_manager.save() try: # if none exists, create a default clock domain and drive it - if clock_domains is None: + if not fragment.clock_domains: if self.default_crg_factory is None: raise NotImplementedError("No clock/reset generator defined by either platform or user") crg = self.default_crg_factory(self) frag = fragment + crg.get_fragment() - clock_domains = crg.get_clock_domains() else: frag = fragment # generate Verilog - src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), - clock_domains=clock_domains, return_ns=True, **kwargs) + src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, **kwargs) # resolve signal names in constraints sc = self.constraint_manager.get_sig_constraints() named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] @@ -230,7 +228,7 @@ class GenericPlatform: self.constraint_manager.restore(backup) return src, named_sc, named_pc - def build(self, fragment, clock_domains=None): + def build(self, fragment): raise NotImplementedError("GenericPlatform.build must be overloaded") def add_arguments(self, parser): diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 698d0b04f..dd3d32630 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -3,10 +3,11 @@ from decimal import Decimal from migen.fhdl.structure import * from migen.fhdl.specials import Instance, SynthesisDirective +from migen.fhdl.module import Module from migen.genlib.cdc import * from mibuild.generic_platform import * -from mibuild.crg import CRG, SimpleCRG +from mibuild.crg import SimpleCRG from mibuild import tools def _add_period_constraint(platform, clk, period): @@ -18,20 +19,21 @@ class CRG_SE(SimpleCRG): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) _add_period_constraint(platform, self.cd.clk, period) -class CRG_DS(CRG): - def __init__(self, platform, clk_name, rst_name, period): - self.cd = ClockDomain("sys") +class CRG_DS(Module): + def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + self.clock_domains.cd_sys = ClockDomain() self._clk = platform.request(clk_name) - platform.request(rst_name, None, self.cd.rst) + if rst_invert: + rst_n = platform.request(rst_name) + self.comb += self.cd_sys.rst.eq(~rst_n) + else: + platform.request(rst_name, None, self.cd.rst) _add_period_constraint(platform, self._clk.p, period) - - def get_fragment(self): - ibufg = Instance("IBUFGDS", + self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), Instance.Input("IB", self._clk.n), Instance.Output("O", self.cd.clk) ) - return Fragment(specials={ibufg}) def _format_constraint(c): if isinstance(c, Pins): @@ -127,12 +129,12 @@ class XilinxISEPlatform(GenericPlatform): so.update(special_overrides) return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) - def build(self, fragment, clock_domains=None, build_dir="build", build_name="top", + def build(self, fragment, build_dir="build", build_name="top", ise_path="/opt/Xilinx", run=True): tools.mkdir_noerror(build_dir) os.chdir(build_dir) - v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains) + v_src, named_sc, named_pc = self.get_verilog(fragment) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")] From 4bf31902441d8713a8c24dfbe596843dbaa5562a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 19:54:25 +0100 Subject: [PATCH 33/83] MultiReg: remove idomain --- mibuild/xilinx_ise.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index dd3d32630..fe76b2ec6 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -121,7 +121,7 @@ class XilinxMultiRegImpl(MultiRegImpl): class XilinxMultiReg: @staticmethod def lower(dr): - return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n) + return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n) class XilinxISEPlatform(GenericPlatform): def get_verilog(self, *args, special_overrides=dict(), **kwargs): From 797411c1a9bc0c0a90a0d0cb0ed867d3bb7c12ee Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 18 Mar 2013 18:44:58 +0100 Subject: [PATCH 34/83] generic_platform: do not create clock domains during Verilog conversion --- mibuild/generic_platform.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index d3fe50b22..fcbe7ba3f 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -214,7 +214,8 @@ class GenericPlatform: else: frag = fragment # generate Verilog - src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, **kwargs) + src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), + return_ns=True, create_clock_domains=False, **kwargs) # resolve signal names in constraints sc = self.constraint_manager.get_sig_constraints() named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] From 003f1950cdefd9decd3569ce3db6bf6caa9db68a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 23 Mar 2013 19:37:16 +0100 Subject: [PATCH 35/83] xilinx_ise: fix clock domain names --- mibuild/xilinx_ise.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index fe76b2ec6..7d194c53f 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self.cd.clk, period) + _add_period_constraint(platform, self.cd_sys.clk, period) class CRG_DS(Module): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): @@ -27,12 +27,12 @@ class CRG_DS(Module): rst_n = platform.request(rst_name) self.comb += self.cd_sys.rst.eq(~rst_n) else: - platform.request(rst_name, None, self.cd.rst) + platform.request(rst_name, None, self.cd_sys.rst) _add_period_constraint(platform, self._clk.p, period) self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), Instance.Input("IB", self._clk.n), - Instance.Output("O", self.cd.clk) + Instance.Output("O", self.cd_sys.clk) ) def _format_constraint(c): From 74cc4d22cd2a582800369b7eba56313bcc2ca4c4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 26 Mar 2013 17:56:53 +0100 Subject: [PATCH 36/83] generic_platform: remove obj in request + add lookup_request --- mibuild/generic_platform.py | 90 +++++++++++++------------------------ 1 file changed, 32 insertions(+), 58 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index fcbe7ba3f..e34360450 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -37,7 +37,7 @@ def _lookup(description, name, number): return resource raise ConstraintError("Resource not found: " + name + ":" + str(number)) -def _resource_type(resource, name_map): +def _resource_type(resource): t = None for element in resource[2:]: if isinstance(element, Pins): @@ -52,29 +52,9 @@ def _resource_type(resource, name_map): if isinstance(c, Pins): assert(n_bits is None) n_bits = len(c.identifiers) - t.append((name_map(element.name), n_bits)) + t.append((element.name, n_bits)) return t -def _match(description, requests): - available = list(description) - matched = [] - - # 1. Match requests for a specific number - for request in requests: - if request[1] is not None: - resource = _lookup(available, request[0], request[1]) - available.remove(resource) - matched.append((resource, request[2], request[3])) - - # 2. Match requests for no specific number - for request in requests: - if request[1] is None: - resource = _lookup(available, request[0], request[1]) - available.remove(resource) - matched.append((resource, request[2], request[3])) - - return matched - def _separate_pins(constraints): pins = None others = [] @@ -88,51 +68,42 @@ def _separate_pins(constraints): class ConstraintManager: def __init__(self, description): - self.description = description - self.requests = [] + self.available = list(description) + self.matched = [] self.platform_commands = [] - self.io_signals = set() - def request(self, name, number=None, obj=None, name_map=lambda s: s): - r = _lookup(self.description, name, number) - t = _resource_type(r, name_map) - - # If obj is None, then create it. - # If it already exists, do some sanity checking. - # Update io_signals at the same time. - if obj is None: - if isinstance(t, int): - obj = Signal(t, name_override=name_map(r[0])) - self.io_signals.add(obj) - else: - obj = Record(t, name=r[0]) - for sig in obj.flatten(): - self.io_signals.add(sig) + def request(self, name, number=None): + resource = _lookup(self.available, name, number) + rt = _resource_type(resource) + if isinstance(rt, int): + obj = Signal(rt, name_override=resource[0]) else: - if isinstance(t, int): - assert(isinstance(obj, Signal) and obj.nbits == t) - self.io_signals.add(obj) - else: - for attr, nbits in t: - sig = getattr(obj, attr) - assert(isinstance(sig, Signal) and sig.nbits == nbits) - self.io_signals.add(sig) - - # Register the request - self.requests.append((name, number, obj, name_map)) - + obj = Record(rt, name=resource[0]) + self.available.remove(resource) + self.matched.append((resource, obj)) return obj + + def lookup_request(self, name, number=None): + for resource, obj in self.matched: + if resource[0] == name and (number is None or resource[1] == number): + return obj + raise ConstraintError("Resource not found: " + name + ":" + str(number)) def add_platform_command(self, command, **signals): self.platform_commands.append((command, signals)) def get_io_signals(self): - return self.io_signals + r = set() + for resource, obj in self.matched: + if isinstance(obj, Signal): + r.add(obj) + else: + r.update(obj.flatten()) + return r def get_sig_constraints(self): r = [] - matched = _match(self.description, self.requests) - for resource, obj, name_map in matched: + for resource, obj in self.matched: name = resource[0] number = resource[1] has_subsignals = False @@ -145,7 +116,7 @@ class ConstraintManager: if has_subsignals: for element in resource[2:]: if isinstance(element, Subsignal): - sig = getattr(obj, name_map(element.name)) + sig = getattr(obj, element.name) pins, others = _separate_pins(top_constraints + element.constraints) r.append((sig, pins, others, (name, number, element.name))) else: @@ -157,10 +128,10 @@ class ConstraintManager: return self.platform_commands def save(self): - return copy(self.requests), copy(self.platform_commands), copy(self.io_signals) + return copy(self.available), copy(self.matched), copy(self.platform_commands) def restore(self, backup): - self.request, self.platform_commands, self.io_signals = backup + self.available, self.matched, self.platform_commands = backup class GenericPlatform: def __init__(self, device, io, default_crg_factory=None, name=None): @@ -175,6 +146,9 @@ class GenericPlatform: def request(self, *args, **kwargs): return self.constraint_manager.request(*args, **kwargs) + def lookup_request(self, *args, **kwargs): + return self.constraint_manager.lookup_request(*args, **kwargs) + def add_platform_command(self, *args, **kwargs): return self.constraint_manager.add_platform_command(*args, **kwargs) From 3b19dfc412137393f1f3d3d5907f3aca05c21bd8 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 26 Mar 2013 19:17:35 +0100 Subject: [PATCH 37/83] Support for platform info --- mibuild/generic_platform.py | 8 ++++++++ mibuild/xilinx_ise.py | 6 +++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index e34360450..3ff2f02e7 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -31,6 +31,10 @@ class Subsignal: self.name = name self.constraints = list(constraints) +class PlatformInfo: + def __init__(self, info): + self.info = info + def _lookup(description, name, number): for resource in description: if resource[0] == name and (number is None or resource[1] == number): @@ -79,6 +83,10 @@ class ConstraintManager: obj = Signal(rt, name_override=resource[0]) else: obj = Record(rt, name=resource[0]) + for element in resource[2:]: + if isinstance(element, PlatformInfo): + obj.platform_info = element.info + break self.available.remove(resource) self.matched.append((resource, obj)) return obj diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 7d194c53f..cddbbb81e 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -46,7 +46,11 @@ def _format_constraint(c): return c.misc def _format_ucf(signame, pin, others, resname): - fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)] + fmt_c = [] + for c in [Pins(pin)] + others: + fc = _format_constraint(c) + if fc is not None: + fmt_c.append(fc) fmt_r = resname[0] + ":" + str(resname[1]) if resname[2] is not None: fmt_r += "." + resname[2] From 38e92eb92b28bd0605a6bd52c8ccf353a5729ef6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 26 Mar 2013 23:05:46 +0100 Subject: [PATCH 38/83] altera_quartus: fix clock domain name --- mibuild/altera_quartus.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index f1d366dfa..4fc785509 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -14,7 +14,7 @@ def _add_period_constraint(platform, clk, period): class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self.cd.clk, period) + _add_period_constraint(platform, self.cd_sys.clk, period) def _format_constraint(c): if isinstance(c, Pins): From 8cf7c96a53bc5edb38fa18461a029e66e5644792 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 26 Mar 2013 23:08:35 +0100 Subject: [PATCH 39/83] crg: use new platform.request --- mibuild/crg.py | 7 +++---- mibuild/xilinx_ise.py | 5 ++--- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/mibuild/crg.py b/mibuild/crg.py index 5d8510dd7..7d967742a 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -4,9 +4,8 @@ from migen.fhdl.module import Module class SimpleCRG(Module): def __init__(self, platform, clk_name, rst_name, rst_invert=False): self.clock_domains.cd_sys = ClockDomain() - platform.request(clk_name, None, self.cd_sys.clk) + self.comb += self.cd_sys.clk.eq(platform.request(clk_name)) if rst_invert: - rst_n = platform.request(rst_name) - self.comb += self.cd_sys.rst.eq(~rst_n) + self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) else: - platform.request(rst_name, None, self.cd_sys.rst) + self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index cddbbb81e..6a1e9d7ed 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -24,10 +24,9 @@ class CRG_DS(Module): self.clock_domains.cd_sys = ClockDomain() self._clk = platform.request(clk_name) if rst_invert: - rst_n = platform.request(rst_name) - self.comb += self.cd_sys.rst.eq(~rst_n) + self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) else: - platform.request(rst_name, None, self.cd_sys.rst) + self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) _add_period_constraint(platform, self._clk.p, period) self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), From 715d332c3d76b89053e15259accc4c4ae979e51b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 8 Apr 2013 20:28:11 +0200 Subject: [PATCH 40/83] crg: apply constraint to IO pins, not internal signals --- mibuild/crg.py | 8 +++++--- mibuild/xilinx_ise.py | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/mibuild/crg.py b/mibuild/crg.py index 7d967742a..83ae9c4e5 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -3,9 +3,11 @@ from migen.fhdl.module import Module class SimpleCRG(Module): def __init__(self, platform, clk_name, rst_name, rst_invert=False): + self._clk = platform.request(clk_name) + self._rst = platform.request(rst_name) self.clock_domains.cd_sys = ClockDomain() - self.comb += self.cd_sys.clk.eq(platform.request(clk_name)) + self.comb += self.cd_sys.clk.eq(self._clk) if rst_invert: - self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) + self.comb += self.cd_sys.rst.eq(~self._rst) else: - self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) + self.comb += self.cd_sys.rst.eq(self._rst) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 6a1e9d7ed..a6c31c00c 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self.cd_sys.clk, period) + _add_period_constraint(platform, self._clk, period) class CRG_DS(Module): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): From 843f8a5bfc9c1e1e747fdeb16f8dbd3eee83b1f2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 8 Apr 2013 20:28:23 +0200 Subject: [PATCH 41/83] platforms: add Papilio Pro --- mibuild/platforms/papilio_pro.py | 45 ++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 mibuild/platforms/papilio_pro.py diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py new file mode 100644 index 000000000..ef11ba408 --- /dev/null +++ b/mibuild/platforms/papilio_pro.py @@ -0,0 +1,45 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE + +_io = [ + ("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + + ("user_btn", 0, Pins("P114"), IOStandard("LVCMOS33")), # C0 + ("user_btn", 1, Pins("P115"), IOStandard("LVCMOS33")), # C1 + + ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), + + ("serial", 0, + Subsignal("tx", Pins("P101"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("P105"), IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + ("spiflash", 0, + Subsignal("cs", Pins("P38")), + Subsignal("clk", Pins("P70")), + Subsignal("mosi", Pins("P64")), + Subsignal("miso", Pins("P65"), Misc("PULLUP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + + ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + ("sdram", 0, + Subsignal("a", Pins("P140", "P139", "P138", "P137", "P46", "P45", "P44", + "P43", "P41", "P40", "P141", "P35", "P34")), + Subsignal("ba", Pins("P143", "P142")), + Subsignal("cs_n", Pins("P1")), + Subsignal("cke", Pins("P33")), + Subsignal("ras_n", Pins("P2")), + Subsignal("cas_n", Pins("P5")), + Subsignal("we_n", Pins("P6")), + Subsignal("dq", Pins("P9", "P10", "P11", "P12", "P14", "P15", "P16", "P8", + "P21", "P22", "P23", "P24", "P26", "P27", "P29", "P30")), + Subsignal("dm", Pins("P7", "P17")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, + lambda p: CRG_SE(p, "clk32", "user_btn", 31.25)) From 59d64e92e84239ab444c44c8a91af6a5ccd07291 Mon Sep 17 00:00:00 2001 From: Werner Almesberger Date: Thu, 11 Apr 2013 21:37:28 -0300 Subject: [PATCH 42/83] mibuild: define memory card pins of the Milkymist One platorm This patch adds the memory card pins to the M1 platform definition in mibuild. I've tentatively named them "mmc". As far as I can tell, "MMC" is not trademarked ("MultiMediaCard" the new "eMMC" would be), and "MMC" is commonly used in the industry in a descriptive way to refer to this sort of interface. The original Verilog-based M1 calls the interface "mc", but since several names have changed between milkymist and -ng, I thought I'd use a more familiar name. Usage example (clock signal divided by powers of two on the MMC TPs): https://github.com/wpwrak/ming-ddc-debug/blob/counter-on-mmc/build.py - Werner --- mibuild/platforms/m1.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 5273441a9..cc29a02f1 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -83,6 +83,13 @@ _io = [ IOStandard("LVCMOS33") ), + ("mmc", 0, + Subsignal("clk", Pins("A10")), + Subsignal("cmd", Pins("B18")), + Subsignal("dat", Pins("A18", "E16", "C17", "A17")), + IOStandard("LVCMOS33") + ), + # Digital video mixer extension board ("dvi_in", 0, Subsignal("clk", Pins("A20")), From 31b1960188f58d55cd3784f1d2d295db8f37ad22 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 16 Apr 2013 22:39:35 +0200 Subject: [PATCH 43/83] xilinx_ise: add --no-source option to disable sourcing of ISE settings file --- mibuild/xilinx_ise.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index a6c31c00c..0d7a663be 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -85,29 +85,28 @@ def _build_files(device, sources, named_sc, named_pc, build_name): -p %s""" % (build_name, build_name, device) tools.write_to_file(build_name + ".xst", xst_contents) -def _run_ise(build_name, ise_path): +def _run_ise(build_name, ise_path, source): def is_valid_version(v): try: Decimal(v) return os.path.isdir(os.path.join(ise_path, v)) except: return False - vers = [ver for ver in os.listdir(ise_path) if is_valid_version(ver)] - tools_version = max(vers) - bits = struct.calcsize("P")*8 - xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) + build_script_contents = "# Autogenerated by mibuild\nset -e\n" + if source: + vers = [ver for ver in os.listdir(ise_path) if is_valid_version(ver)] + tools_version = max(vers) + bits = struct.calcsize("P")*8 + xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) + build_script_contents += "source " + xilinx_settings_file + "\n" - build_script_contents = """# Autogenerated by mibuild - -set -e - -source {xilinx_settings_file} + build_script_contents += """ xst -ifn {build_name}.xst ngdbuild -uc {build_name}.ucf {build_name}.ngc map -ol high -w {build_name}.ngd par -ol high -w {build_name}.ncd {build_name}-routed.ncd bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit -""".format(build_name=build_name, xilinx_settings_file=xilinx_settings_file) +""".format(build_name=build_name) build_script_file = "build_" + build_name + ".sh" tools.write_to_file(build_script_file, build_script_contents) @@ -133,7 +132,7 @@ class XilinxISEPlatform(GenericPlatform): return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) def build(self, fragment, build_dir="build", build_name="top", - ise_path="/opt/Xilinx", run=True): + ise_path="/opt/Xilinx", source=True, run=True): tools.mkdir_noerror(build_dir) os.chdir(build_dir) @@ -143,13 +142,14 @@ class XilinxISEPlatform(GenericPlatform): sources = self.sources + [(v_file, "verilog")] _build_files(self.device, sources, named_sc, named_pc, build_name) if run: - _run_ise(build_name, ise_path) + _run_ise(build_name, ise_path, source) os.chdir("..") def build_arg_ns(self, ns, *args, **kwargs): for n in ["build_dir", "build_name", "ise_path"]: kwargs[n] = getattr(ns, n) + kwargs["source"] = not ns.no_source kwargs["run"] = not ns.no_run self.build(*args, **kwargs) @@ -157,4 +157,5 @@ class XilinxISEPlatform(GenericPlatform): parser.add_argument("--build-dir", default="build", help="Set the directory in which to generate files and run ISE") parser.add_argument("--build-name", default="top", help="Base name for the generated files") parser.add_argument("--ise-path", default="/opt/Xilinx", help="ISE installation path (without version directory)") + parser.add_argument("--no-source", action="store_true", help="Do not source ISE settings file") parser.add_argument("--no-run", action="store_true", help="Only generate files, do not run ISE") From 29eaf068f384d08b128bed213483318ce1691246 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 16 Apr 2013 22:55:24 +0200 Subject: [PATCH 44/83] xilinx_ise: do not attempt to source settings file on Windows --- mibuild/xilinx_ise.py | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 0d7a663be..fa1eb1b32 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -1,4 +1,4 @@ -import os, struct, subprocess +import os, struct, subprocess, sys from decimal import Decimal from migen.fhdl.structure import * @@ -85,16 +85,19 @@ def _build_files(device, sources, named_sc, named_pc, build_name): -p %s""" % (build_name, build_name, device) tools.write_to_file(build_name + ".xst", xst_contents) +def _is_valid_version(path, v): + try: + Decimal(v) + return os.path.isdir(os.path.join(path, v)) + except: + return False + def _run_ise(build_name, ise_path, source): - def is_valid_version(v): - try: - Decimal(v) - return os.path.isdir(os.path.join(ise_path, v)) - except: - return False + if sys.platform == "win32" or sys.platform == "cygwin": + source = False build_script_contents = "# Autogenerated by mibuild\nset -e\n" if source: - vers = [ver for ver in os.listdir(ise_path) if is_valid_version(ver)] + vers = [ver for ver in os.listdir(ise_path) if _is_valid_version(ise_path, ver)] tools_version = max(vers) bits = struct.calcsize("P")*8 xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) From 6204bcfa100509cb9bb73b5ee49de3316ae4c859 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 19 Apr 2013 14:00:46 +0200 Subject: [PATCH 45/83] README: fix quick intro --- README | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/README b/README index 1e04545c2..ccb46b46d 100644 --- a/README +++ b/README @@ -1,14 +1,18 @@ Mibuild (Milkymist Build system) a build system and board database for Migen-based FPGA designs -6-ligne intro: +Quick intro: from migen.fhdl.structure import * +from migen.fhdl.module import Module from mibuild.platforms import m1 plat = m1.Platform() led = plat.request("user_led") -f = Fragment([led.eq(counter[25])], [counter.eq(counter + 1)]) -plat.build_cmdline(f) +m = Module() +counter = Signal(26) +m.comb += led.eq(counter[25]) +m.sync += counter.eq(counter + 1) +plat.build_cmdline(m) Code repository: https://github.com/milkymist/mibuild From bd0ae6592e620a83689a45ee40dbbfbd5c0ab174 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 19 Apr 2013 14:04:59 +0200 Subject: [PATCH 46/83] Add setup.py --- setup.py | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100755 setup.py diff --git a/setup.py b/setup.py new file mode 100755 index 000000000..246957127 --- /dev/null +++ b/setup.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 + +import sys, os +from setuptools import setup +from setuptools import find_packages + +here = os.path.abspath(os.path.dirname(__file__)) +README = open(os.path.join(here, "README")).read() + +required_version = (3, 1) +if sys.version_info < required_version: + raise SystemExit("Mibuild requires python {0} or greater".format( + ".".join(map(str, required_version)))) + +setup( + name="mibuild", + version="unknown", + description="Build system and board definitions for Migen FPGA designs", + long_description=README, + author="Sebastien Bourdeauducq", + author_email="sebastien@milkymist.org", + url="http://www.milkymist.org", + download_url="https://github.com/milkymist/mibuild", + packages=find_packages(here), + license="GPL", + platforms=["Any"], + keywords="HDL ASIC FPGA hardware design", + classifiers=[ + "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", + "Environment :: Console", + "Development Status :: Alpha", + "Intended Audience :: Developers", + "License :: OSI Approved :: GNU General Public License (GPL)", + "Operating System :: OS Independent", + "Programming Language :: Python", + ], +) From 85e06cc100e90fe23c1032f4d74c7de749970741 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 25 Apr 2013 14:57:45 +0200 Subject: [PATCH 47/83] xilinx_ise: implement NoRetiming synthesis constraint --- mibuild/xilinx_ise.py | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index fa1eb1b32..63e68bfc4 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -117,11 +117,20 @@ bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit if r != 0: raise OSError("Subprocess failed") +class XilinxNoRetimingImpl(Module): + def __init__(self, reg): + self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg) + +class XilinxNoRetiming: + @staticmethod + def lower(dr): + return XilinxNoRetimingImpl(dr.reg) + class XilinxMultiRegImpl(MultiRegImpl): - def get_fragment(self): - disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r) - for r in self.regs) - return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl) + def __init__(self, *args, **kwargs): + MultiRegImpl.__init__(self, *args, **kwargs) + self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r) + for r in self.regs] class XilinxMultiReg: @staticmethod @@ -130,7 +139,10 @@ class XilinxMultiReg: class XilinxISEPlatform(GenericPlatform): def get_verilog(self, *args, special_overrides=dict(), **kwargs): - so = {MultiReg: XilinxMultiReg} + so = { + NoRetiming: XilinxNoRetiming, + MultiReg: XilinxMultiReg + } so.update(special_overrides) return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) From e4b0e8ed6d3397698913ab946c54437107830fd8 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 May 2013 14:21:39 +0200 Subject: [PATCH 48/83] xilinx_ise: enable register balancing --- mibuild/xilinx_ise.py | 1 + 1 file changed, 1 insertion(+) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 63e68bfc4..85d277122 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -81,6 +81,7 @@ def _build_files(device, sources, named_sc, named_pc, build_name): -ifmt MIXED -opt_mode SPEED -reduce_control_sets auto +-register_balancing yes -ofn %s.ngc -p %s""" % (build_name, build_name, device) tools.write_to_file(build_name + ".xst", xst_contents) From 3d0894465c6835f11dfbd49d234062b64d97cba3 Mon Sep 17 00:00:00 2001 From: Brandon Hamilton Date: Mon, 6 May 2013 11:55:30 +0200 Subject: [PATCH 49/83] mibuild: Add platform for Xilinx ML605 board --- mibuild/platforms/ml605.py | 56 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 mibuild/platforms/ml605.py diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py new file mode 100644 index 000000000..73262d033 --- /dev/null +++ b/mibuild/platforms/ml605.py @@ -0,0 +1,56 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS + +_io = [ + # System clock (Differential 200MHz) + ("clk200", 0, + Subsignal("p", Pins("J9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), + Subsignal("n", Pins("H9"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")) + ), + + # User clock (66MHz) + ("clk66", 0, Pins("U23"), IOStandard("LVCMOS25")), + + # CPU reset switch + ("cpu_reset", 0, Pins("H10"), IOStandard("SSTL15")), + + # LEDs + ("user_led", 0, Pins("AC22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 1, Pins("AC24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 2, Pins("AE22"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 3, Pins("AE23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 4, Pins("AB23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 5, Pins("AG23"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 6, Pins("AE24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + ("user_led", 7, Pins("AD24"), IOStandard("LVCMOS25"), Misc("SLEW=SLOW")), + + # USB-to-UART + ("serial", 0, + Subsignal("tx", Pins("J25"), IOStandard("LVCMOS25")), + Subsignal("rx", Pins("J24"), IOStandard("LVCMOS25")) + ), + + # 10/100/1000 Tri-Speed Ethernet PHY + ("eth_clocks", 0, + Subsignal("rx", Pins("AP11")), + Subsignal("tx", Pins("AD12")), + IOStandard("LVCMOS25") + ), + ("eth", 0, + Subsignal("rst_n", Pins("AH13")), + Subsignal("dv", Pins("AM13")), + Subsignal("rx_er", Pins("AG12")), + Subsignal("rx_data", Pins("AN13", "AF14", "AE14", "AN12", "AM12", "AD11", "AC12", "AC13")), + Subsignal("tx_en", Pins("AJ10")), + Subsignal("tx_er", Pins("AH10")), + Subsignal("tx_data", Pins("AM11", "AL11", "AG10", "AG11", "AL10", "AM10", "AE11", "AF11")), + Subsignal("col", Pins("AK13")), + Subsignal("crs", Pins("AL13")), + IOStandard("LVCMOS25") + ) +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io, + lambda p: CRG_DS(p, "clk200", "user_btn", 5.0)) From 6a4c194aabd364945d8fb813de9abfdfe498bb22 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 7 May 2013 10:30:56 +0200 Subject: [PATCH 50/83] platforms: add KC705 --- mibuild/platforms/kc705.py | 88 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 mibuild/platforms/kc705.py diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py new file mode 100644 index 000000000..c299e2b56 --- /dev/null +++ b/mibuild/platforms/kc705.py @@ -0,0 +1,88 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_DS + +_io = [ + ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), + ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), + ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), + ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), + ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")), + ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), + ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), + ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), + + ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), + + ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), + ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")), + ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")), + ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), + ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), + + ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), + ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), + ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")), + ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), + + ("clk200", 0, + Subsignal("p", Pins("AD12"), IOStandard("LVDS")), + Subsignal("n", Pins("AD11"), IOStandard("LVDS")) + ), + + ("clk156", 0, + Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), + Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) + ), + + ("i2c", 0, + Subsignal("scl", Pins("K21")), + Subsignal("sda", Pins("L21")), + IOStandard("LVCMOS25")), + + ("serial", 0, + Subsignal("cts", Pins("L27")), + Subsignal("rts", Pins("K23")), + Subsignal("tx", Pins("K24")), + Subsignal("rx", Pins("M19")), + IOStandard("LVCMOS25")), + + ("mmc", 0, + Subsignal("wp", Pins("Y21")), + Subsignal("det", Pins("AA21")), + Subsignal("cmd", Pins("AB22")), + Subsignal("clk", Pins("AB23")), + Subsignal("dat", Pins("AC20", "AA23", "AA22", "AC21")), + IOStandard("LVCMOS25")), + + ("lcd", 0, + Subsignal("db", Pins("AA13", "AA10", "AA11", "Y10")), + Subsignal("e", Pins("AB10")), + Subsignal("rs", Pins("Y11")), + Subsignal("rw", Pins("AB13")), + IOStandard("LVCMOS15")), + + ("rotary", 0, + Subsignal("a", Pins("Y26")), + Subsignal("b", Pins("Y25")), + Subsignal("push", Pins("AA26")), + IOStandard("LVCMOS25")), + + ("hdmi", 0, + Subsignal("d", Pins("B23", "A23", "E23", "D23", + "F25", "E25", "E24", "D24", + "F26", "E26", "G23", "G24", + "J19", "H19", "L17", "L18", + "K19", "K20")), + Subsignal("de", Pins("H17")), + Subsignal("clk", Pins("K18")), + Subsignal("vsync", Pins("H20")), + Subsignal("hsync", Pins("J18")), + Subsignal("int", Pins("AH24")), + Subsignal("spdif", Pins("J17")), + Subsignal("spdif_out", Pins("G20")), + IOStandard("LVCMOS25")), +] + +class Platform(XilinxISEPlatform): + def __init__(self, crg_factory=lambda p: CRG_DS(p, "user_clk", "cpu_reset", 6.4)): + XilinxISEPlatform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory) From 439f032921e3ddc1c1e3b13288f0d024aaa009ac Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 7 May 2013 19:09:56 +0200 Subject: [PATCH 51/83] crg: support for resetless system clock domain --- mibuild/crg.py | 14 ++++++++------ mibuild/xilinx_ise.py | 12 +++++++----- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/mibuild/crg.py b/mibuild/crg.py index 83ae9c4e5..7b5799f36 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -3,11 +3,13 @@ from migen.fhdl.module import Module class SimpleCRG(Module): def __init__(self, platform, clk_name, rst_name, rst_invert=False): + reset_less = rst_name is None + self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) self._clk = platform.request(clk_name) - self._rst = platform.request(rst_name) - self.clock_domains.cd_sys = ClockDomain() self.comb += self.cd_sys.clk.eq(self._clk) - if rst_invert: - self.comb += self.cd_sys.rst.eq(~self._rst) - else: - self.comb += self.cd_sys.rst.eq(self._rst) + + if not reset_less: + if rst_invert: + self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) + else: + self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 85d277122..d6ac47291 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -21,18 +21,20 @@ class CRG_SE(SimpleCRG): class CRG_DS(Module): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): - self.clock_domains.cd_sys = ClockDomain() + reset_less = rst_name is None + self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) self._clk = platform.request(clk_name) - if rst_invert: - self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) - else: - self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) _add_period_constraint(platform, self._clk.p, period) self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), Instance.Input("IB", self._clk.n), Instance.Output("O", self.cd_sys.clk) ) + if not reset_less: + if rst_invert: + self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) + else: + self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) def _format_constraint(c): if isinstance(c, Pins): From 7a2f31b2e8880f9ec8e13f416cf35a27f734f1e6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 7 May 2013 19:10:18 +0200 Subject: [PATCH 52/83] platforms/papilio_pro: no reset signal by default --- mibuild/platforms/papilio_pro.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index ef11ba408..eebf66343 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -42,4 +42,4 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, - lambda p: CRG_SE(p, "clk32", "user_btn", 31.25)) + lambda p: CRG_SE(p, "clk32", None, 31.25)) From fe64ade1ac342bd70bcbe034862fa24074d8dbed Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 13 May 2013 15:38:20 +0200 Subject: [PATCH 53/83] platforms/m1: add pots pins --- mibuild/platforms/m1.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index cc29a02f1..e745968c2 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -108,6 +108,12 @@ _io = [ Subsignal("scl", Pins("J16")), Subsignal("sda", Pins("K16")), IOStandard("LVCMOS33") + ), + ("dvi_pots", 0, + Subsignal("charge", Pins("A18")), # SD_DAT0 + Subsignal("blackout", Pins("C17")), # SD_DAT2 + Subsignal("crossfade", Pins("A17")), # SD_DAT3 + IOStandard("LVCMOS33") ) ] From e272e68facceca3e9a8a3abe684d4b8d29c5b831 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 19 May 2013 20:24:47 +0200 Subject: [PATCH 54/83] platforms/papilio_pro: swap tx/rx to be consistent with M1 --- mibuild/platforms/papilio_pro.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index eebf66343..e7b3a71de 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -10,8 +10,8 @@ _io = [ ("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")), ("serial", 0, - Subsignal("tx", Pins("P101"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), - Subsignal("rx", Pins("P105"), IOStandard("LVCMOS33"), Misc("PULLUP")) + Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP")) ), ("spiflash", 0, From c13e573e9f39d329b5aa96b47842592972c6e043 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 26 May 2013 18:02:18 +0200 Subject: [PATCH 55/83] Require Python 3.3 --- README | 2 +- setup.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/README b/README index ccb46b46d..09e29e1d4 100644 --- a/README +++ b/README @@ -21,7 +21,7 @@ https://github.com/milkymist/migen Experimental version of the Milkymist SoC based on Migen: https://github.com/milkymist/milkymist-ng -Mibuild is designed for Python 3. +Mibuild is designed for Python 3.3. Send questions, comments and patches to devel [AT] lists.milkymist.org Description files for new boards welcome. diff --git a/setup.py b/setup.py index 246957127..76cc0bc46 100755 --- a/setup.py +++ b/setup.py @@ -7,7 +7,7 @@ from setuptools import find_packages here = os.path.abspath(os.path.dirname(__file__)) README = open(os.path.join(here, "README")).read() -required_version = (3, 1) +required_version = (3, 3) if sys.version_info < required_version: raise SystemExit("Mibuild requires python {0} or greater".format( ".".join(map(str, required_version)))) From 759858f7398094f26a89be802e942c9da021c55f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 26 May 2013 18:07:26 +0200 Subject: [PATCH 56/83] Use migen.fhdl.std --- README | 3 +-- mibuild/crg.py | 3 +-- mibuild/generic_platform.py | 2 +- mibuild/xilinx_ise.py | 5 ++--- 4 files changed, 5 insertions(+), 8 deletions(-) diff --git a/README b/README index 09e29e1d4..d649b4b19 100644 --- a/README +++ b/README @@ -3,8 +3,7 @@ Mibuild (Milkymist Build system) Quick intro: -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from mibuild.platforms import m1 plat = m1.Platform() led = plat.request("user_led") diff --git a/mibuild/crg.py b/mibuild/crg.py index 7b5799f36..5d51a13b9 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * class SimpleCRG(Module): def __init__(self, platform, clk_name, rst_name, rst_invert=False): diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 3ff2f02e7..2ce4673bd 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -1,7 +1,7 @@ from copy import copy import os, argparse -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.genlib.record import Record from migen.fhdl import verilog diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index d6ac47291..c5273cabd 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -1,9 +1,8 @@ import os, struct, subprocess, sys from decimal import Decimal -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance, SynthesisDirective -from migen.fhdl.module import Module +from migen.fhdl.std import * +from migen.fhdl.specials import SynthesisDirective from migen.genlib.cdc import * from mibuild.generic_platform import * From 548f2685bb96345c495dad56baaf9ead8455691d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 30 May 2013 11:06:02 +0200 Subject: [PATCH 57/83] platform/rhino: rename ismm data out signal to locked --- mibuild/platforms/rhino.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index eadd135c8..7150c76d1 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -104,7 +104,7 @@ _io = [ Subsignal("enx", Pins("E5")), Subsignal("sclk", Pins("G6")), Subsignal("sdata", Pins("F5")), - Subsignal("sdatao", Pins("E6")), + Subsignal("locked", Pins("E6")), IOStandard("LVCMOS33") ), # RX path @@ -126,7 +126,7 @@ _io = [ Subsignal("enx", Pins("A2")), Subsignal("sclk", Pins("G9")), Subsignal("sdata", Pins("H9")), - Subsignal("sdatao", Pins("A3")), + Subsignal("locked", Pins("A3")), IOStandard("LVCMOS33") ) ] From 953e603915cddfc9d887912391e8fe85b31d3699 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 1 Jun 2013 17:22:57 +0200 Subject: [PATCH 58/83] xilinx_ise: improve parameter passing --- mibuild/xilinx_ise.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index c5273cabd..bb70fdd3c 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -165,14 +165,18 @@ class XilinxISEPlatform(GenericPlatform): def build_arg_ns(self, ns, *args, **kwargs): for n in ["build_dir", "build_name", "ise_path"]: - kwargs[n] = getattr(ns, n) - kwargs["source"] = not ns.no_source - kwargs["run"] = not ns.no_run + attr = getattr(ns, n) + if attr is not None: + kwargs[n] = attr + if ns.no_source: + kwargs["source"] = False + if ns.no_run: + kwargs["run"] = False self.build(*args, **kwargs) def add_arguments(self, parser): - parser.add_argument("--build-dir", default="build", help="Set the directory in which to generate files and run ISE") - parser.add_argument("--build-name", default="top", help="Base name for the generated files") - parser.add_argument("--ise-path", default="/opt/Xilinx", help="ISE installation path (without version directory)") + parser.add_argument("--build-dir", default=None, help="Set the directory in which to generate files and run ISE") + parser.add_argument("--build-name", default=None, help="Base name for the generated files") + parser.add_argument("--ise-path", default=None, help="ISE installation path (without version directory)") parser.add_argument("--no-source", action="store_true", help="Do not source ISE settings file") parser.add_argument("--no-run", action="store_true", help="Only generate files, do not run ISE") From 6b56428a2186cbbf385f1e408492637149d9cb5c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 25 Jun 2013 22:57:31 +0200 Subject: [PATCH 59/83] Shorter multipin signal definition --- mibuild/generic_platform.py | 4 +++- mibuild/platforms/de0nano.py | 27 +++++++++-------------- mibuild/platforms/kc705.py | 10 +++------ mibuild/platforms/m1.py | 37 ++++++++++++++++---------------- mibuild/platforms/ml605.py | 4 ++-- mibuild/platforms/papilio_pro.py | 11 +++++----- mibuild/platforms/rhino.py | 16 +++++++------- mibuild/platforms/roach.py | 12 +++++------ 8 files changed, 55 insertions(+), 66 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 2ce4673bd..482c485e8 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -12,7 +12,9 @@ class ConstraintError(Exception): class Pins: def __init__(self, *identifiers): - self.identifiers = identifiers + self.identifiers = [] + for i in identifiers: + self.identifiers += i.split() class IOStandard: def __init__(self, name): diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index 496591aca..72a109d6b 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -31,16 +31,14 @@ _io = [ ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), ("sdram", 0, - Subsignal("a", Pins("P2", "N5", "N6", "M8", "P8", "T7", "N8", "T6", - "R1", "P1", "N2", "N1", "L4")), - Subsignal("ba", Pins("M7", "M6")), + Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")), + Subsignal("ba", Pins("M7 M6")), Subsignal("cs_n", Pins("P6")), Subsignal("cke", Pins("L7")), Subsignal("ras_n", Pins("L2")), Subsignal("cas_n", Pins("L1")), Subsignal("we_n", Pins("C2")), - Subsignal("dq", Pins("G2", "G1", "L8", "K5", "K2", "J2", "J1", "R7", - "T4", "T2", "T3", "R3", "R5", "P3", "N3", "K1")), + Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")), Subsignal("dqm", Pins("R6","T5")), IOStandard("3.3-V LVTTL") ), @@ -74,24 +72,19 @@ _io = [ ), ("gpio_0", 0, - Pins("D3", "C3", "A2", "A3", "B3", "B4", "A4", "B5", - "A5", "D5", "B6", "A6", "B7", "D6", "A7", "C6", - "C8", "E6", "E7", "D8", "E8", "F8", "F9", "E9", - "C9", "D9", "E11", "E10", "C11", "B11", "A12", "D11", - "D12", "B12"), + Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6", + "C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11", + "D12 B12"), IOStandard("3.3-V LVTTL") ), ("gpio_1", 0, - Pins("F13", "T15", "T14", "T13", "R13", "T12", "R12", "T11", - "T10", "R11", "P11", "R10", "N12", "P9", "N9", "N11", - "L16", "K16", "R16", "L15", "P15", "P16", "R14", "N16", - "N15", "P14", "L14", "N14", "M10", "L13", "J16", "K15", - "J13", "J14"), + Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11", + "L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15", + "J13 J14"), IOStandard("3.3-V LVTTL") ), ("gpio_2", 0, - Pins("A14", "B16", "C14", "C16", "C15", "D16", "D15", "D14", - "F15", "F16", "F14", "G16", "G15"), + Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"), IOStandard("3.3-V LVTTL") ), ] diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index c299e2b56..bb47edccb 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -51,11 +51,11 @@ _io = [ Subsignal("det", Pins("AA21")), Subsignal("cmd", Pins("AB22")), Subsignal("clk", Pins("AB23")), - Subsignal("dat", Pins("AC20", "AA23", "AA22", "AC21")), + Subsignal("dat", Pins("AC20 AA23 AA22 AC21")), IOStandard("LVCMOS25")), ("lcd", 0, - Subsignal("db", Pins("AA13", "AA10", "AA11", "Y10")), + Subsignal("db", Pins("AA13 AA10 AA11 Y10")), Subsignal("e", Pins("AB10")), Subsignal("rs", Pins("Y11")), Subsignal("rw", Pins("AB13")), @@ -68,11 +68,7 @@ _io = [ IOStandard("LVCMOS25")), ("hdmi", 0, - Subsignal("d", Pins("B23", "A23", "E23", "D23", - "F25", "E25", "E24", "D24", - "F26", "E26", "G23", "G24", - "J19", "H19", "L17", "L18", - "K19", "K20")), + Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")), Subsignal("de", Pins("H17")), Subsignal("clk", Pins("K18")), Subsignal("vsync", Pins("H20")), diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index e745968c2..ae391e768 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -15,11 +15,11 @@ _io = [ # the flash reset to be released before the system reset. ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), ("norflash", 0, - Subsignal("adr", Pins("L22", "L20", "K22", "K21", "J19", "H20", "F22", - "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20", - "G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19")), - Subsignal("d", Pins("AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7", - "AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"), Misc("PULLDOWN")), + Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22", + "F21 K17 J17 E22 E20 H18 H19 F20", + "G19 C22 C20 D22 D21 F19 F18 D20 D19")), + Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7", + "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")), Subsignal("oe_n", Pins("M22")), Subsignal("we_n", Pins("N20")), Subsignal("ce_n", Pins("M21")), @@ -37,19 +37,18 @@ _io = [ IOStandard("SSTL2_I") ), ("ddram", 0, - Subsignal("a", Pins("B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5", - "G6", "C1", "C3", "D1", "D2")), - Subsignal("ba", Pins("A2", "E6")), + Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")), + Subsignal("ba", Pins("A2 E6")), Subsignal("cs_n", Pins("F7")), Subsignal("cke", Pins("G7")), Subsignal("ras_n", Pins("E5")), Subsignal("cas_n", Pins("C4")), Subsignal("we_n", Pins("D3")), - Subsignal("dq", Pins("Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3", - "U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4", - "M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1")), - Subsignal("dm", Pins("E1", "E3", "F3", "G4")), - Subsignal("dqs", Pins("F1", "F2", "H5", "H6")), + Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", + "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", + "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")), + Subsignal("dm", Pins("E1 E3 F3 G4")), + Subsignal("dqs", Pins("F1 F2 H5 H6")), IOStandard("SSTL2_I") ), @@ -63,10 +62,10 @@ _io = [ Subsignal("rst_n", Pins("R22")), Subsignal("dv", Pins("V21")), Subsignal("rx_er", Pins("V22")), - Subsignal("rx_data", Pins("U22", "U20", "T22", "T21")), + Subsignal("rx_data", Pins("U22 U20 T22 T21")), Subsignal("tx_en", Pins("N19")), Subsignal("tx_er", Pins("M19")), - Subsignal("tx_data", Pins("M16", "L15", "P19", "P20")), + Subsignal("tx_data", Pins("M16 L15 P19 P20")), Subsignal("col", Pins("W20")), Subsignal("crs", Pins("W22")), IOStandard("LVCMOS33") @@ -74,9 +73,9 @@ _io = [ ("vga_clock", 0, Pins("A11"), IOStandard("LVCMOS33")), ("vga", 0, - Subsignal("r", Pins("C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9")), - Subsignal("g", Pins("C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10")), - Subsignal("b", Pins("D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14")), + Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), + Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), + Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), Subsignal("hsync_n", Pins("A14")), Subsignal("vsync_n", Pins("C15")), Subsignal("psave_n", Pins("B14")), @@ -86,7 +85,7 @@ _io = [ ("mmc", 0, Subsignal("clk", Pins("A10")), Subsignal("cmd", Pins("B18")), - Subsignal("dat", Pins("A18", "E16", "C17", "A17")), + Subsignal("dat", Pins("A18 E16 C17 A17")), IOStandard("LVCMOS33") ), diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py index 73262d033..72c49e670 100644 --- a/mibuild/platforms/ml605.py +++ b/mibuild/platforms/ml605.py @@ -40,10 +40,10 @@ _io = [ Subsignal("rst_n", Pins("AH13")), Subsignal("dv", Pins("AM13")), Subsignal("rx_er", Pins("AG12")), - Subsignal("rx_data", Pins("AN13", "AF14", "AE14", "AN12", "AM12", "AD11", "AC12", "AC13")), + Subsignal("rx_data", Pins("AN13 AF14 AE14 AN12 AM12 AD11 AC12 AC13")), Subsignal("tx_en", Pins("AJ10")), Subsignal("tx_er", Pins("AH10")), - Subsignal("tx_data", Pins("AM11", "AL11", "AG10", "AG11", "AL10", "AM10", "AE11", "AF11")), + Subsignal("tx_data", Pins("AM11 AL11 AG10 AG11 AL10 AM10 AE11 AF11")), Subsignal("col", Pins("AK13")), Subsignal("crs", Pins("AL13")), IOStandard("LVCMOS25") diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index e7b3a71de..7c8a6316e 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -24,17 +24,16 @@ _io = [ ("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram", 0, - Subsignal("a", Pins("P140", "P139", "P138", "P137", "P46", "P45", "P44", - "P43", "P41", "P40", "P141", "P35", "P34")), - Subsignal("ba", Pins("P143", "P142")), + Subsignal("a", Pins("P140 P139 P138 P137 P46 P45 P44", + "P43 P41 P40 P141 P35 P34")), + Subsignal("ba", Pins("P143 P142")), Subsignal("cs_n", Pins("P1")), Subsignal("cke", Pins("P33")), Subsignal("ras_n", Pins("P2")), Subsignal("cas_n", Pins("P5")), Subsignal("we_n", Pins("P6")), - Subsignal("dq", Pins("P9", "P10", "P11", "P12", "P14", "P15", "P16", "P8", - "P21", "P22", "P23", "P24", "P26", "P27", "P29", "P30")), - Subsignal("dm", Pins("P7", "P17")), + Subsignal("dq", Pins("P9 P10 P11 P12 P14 P15 P16 P8 P21 P22 P23 P24 P26 P27 P29 P30")), + Subsignal("dm", Pins("P7 P17")), IOStandard("LVCMOS33"), Misc("SLEW=FAST") ), ] diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index 7150c76d1..4609d1bb8 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -20,8 +20,8 @@ _io = [ ("gpmc", 0, Subsignal("clk", Pins("R26")), - Subsignal("a", Pins("N17", "N18", "L23", "L24", "N19", "N20", "N21", "N22", "P17", "P19")), - Subsignal("d", Pins("N23", "N24", "R18", "R19", "P21", "P22", "R20", "R21", "P24", "P26", "R23", "R24", "T22", "T23", "U23", "R25")), + Subsignal("a", Pins("N17 N18 L23 L24 N19 N20 N21 N22 P17 P19")), + Subsignal("d", Pins("N23 N24 R18 R19 P21 P22 R20 R21 P24 P26 R23 R24 T22 T23 U23 R25")), Subsignal("we_n", Pins("W26")), Subsignal("oe_n", Pins("AA25")), Subsignal("ale_n", Pins("AA26")), @@ -63,17 +63,17 @@ _io = [ Subsignal("pg_c2m", Pins("AA23"), IOStandard("LVCMOS33")) ), ("ti_dac", 0, # DAC3283 - Subsignal("dat_p", Pins("AA10", "AA9", "V11", "Y11", "W14", "Y12", "AD14", "AE13"), IOStandard("LVDS_25")), - Subsignal("dat_n", Pins("AB11", "AB9", "V10", "AA11", "Y13", "AA12", "AF14", "AF13"), IOStandard("LVDS_25")), + Subsignal("dat_p", Pins("AA10 AA9 V11 Y11 W14 Y12 AD14 AE13"), IOStandard("LVDS_25")), + Subsignal("dat_n", Pins("AB11 AB9 V10 AA11 Y13 AA12 AF14 AF13"), IOStandard("LVDS_25")), Subsignal("frame_p", Pins("AB13"), IOStandard("LVDS_25")), Subsignal("frame_n", Pins("AA13"), IOStandard("LVDS_25")), Subsignal("txenable", Pins("AB15"), IOStandard("LVCMOS25")) ), ("ti_adc", 0, # ADS62P49 - Subsignal("dat_a_p", Pins("AB14", "Y21", "W20", "AB22", "V18", "W17", "AA21")), - Subsignal("dat_a_n", Pins("AC14", "AA22", "Y20", "AC22", "W19", "W18", "AB21")), - Subsignal("dat_b_p", Pins("Y17", "U15", "AA19", "W16", "AA18", "Y15", "V14")), - Subsignal("dat_b_n", Pins("AA17", "V16", "AB19", "Y16", "AB17", "AA16", "V15")), + Subsignal("dat_a_p", Pins("AB14 Y21 W20 AB22 V18 W17 AA21")), + Subsignal("dat_a_n", Pins("AC14 AA22 Y20 AC22 W19 W18 AB21")), + Subsignal("dat_b_p", Pins("Y17 U15 AA19 W16 AA18 Y15 V14")), + Subsignal("dat_b_n", Pins("AA17 V16 AB19 Y16 AB17 AA16 V15")), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") ), ("fmc150_clocks", 0, diff --git a/mibuild/platforms/roach.py b/mibuild/platforms/roach.py index de46fcc78..a23bd90f7 100644 --- a/mibuild/platforms/roach.py +++ b/mibuild/platforms/roach.py @@ -5,13 +5,13 @@ _io = [ ("epb", 0, Subsignal("cs_n", Pins("K13")), Subsignal("r_w_n", Pins("AF20")), - Subsignal("be_n", Pins("AF14", "AF18")), + Subsignal("be_n", Pins("AF14 AF18")), Subsignal("oe_n", Pins("AF21")), - Subsignal("addr", Pins("AE23", "AE22", "AG18", "AG12", "AG15", "AG23", "AF19", "AE12", "AG16", "AF13", "AG20", "AF23", - "AH17", "AH15", "L20", "J22", "H22", "L15", "L16", "K22", "K21", "K16", "J15")), - Subsignal("addr_gp", Pins("L21", "G22", "K23", "K14", "L14", "J12")), - Subsignal("data", Pins("AF15", "AE16", "AE21", "AD20", "AF16", "AE17", "AE19", "AD19", "AG22", "AH22", "AH12", "AG13", - "AH20", "AH19", "AH14", "AH13")), + Subsignal("addr", Pins("AE23 AE22 AG18 AG12 AG15 AG23 AF19 AE12 AG16 AF13 AG20 AF23", + "AH17 AH15 L20 J22 H22 L15 L16 K22 K21 K16 J15")), + Subsignal("addr_gp", Pins("L21 G22 K23 K14 L14 J12")), + Subsignal("data", Pins("AF15 AE16 AE21 AD20 AF16 AE17 AE19 AD19 AG22 AH22 AH12 AG13", + "AH20 AH19 AH14 AH13")), Subsignal("rdy", Pins("K12")), IOStandard("LVCMOS33") ), From e233c62d276908c0aea8f6982711ee277c679ec4 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 25 Jun 2013 16:27:41 -0600 Subject: [PATCH 60/83] * generic_platform.py: add a finalize() method ... to add e.g. timing constraints after the other modules have had their say and when the signal names are known --- mibuild/altera_quartus.py | 1 + mibuild/generic_platform.py | 12 ++++++++++++ mibuild/xilinx_ise.py | 1 + 3 files changed, 14 insertions(+) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 4fc785509..dbb336a75 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -74,6 +74,7 @@ quartus_sta {build_name}.qpf class AlteraQuartusPlatform(GenericPlatform): def build(self, fragment, build_dir="build", build_name="top", quartus_path="/opt/Altera", run=True): + self.finalize(fragment) tools.mkdir_noerror(build_dir) os.chdir(build_dir) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 482c485e8..2feb70e4d 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -152,6 +152,7 @@ class GenericPlatform: name = self.__module__.split(".")[-1] self.name = name self.sources = [] + self.finalized = False def request(self, *args, **kwargs): return self.constraint_manager.request(*args, **kwargs) @@ -162,6 +163,17 @@ class GenericPlatform: def add_platform_command(self, *args, **kwargs): return self.constraint_manager.add_platform_command(*args, **kwargs) + def finalize(self, fragment, *args, **kwargs): + if self.finalized: + raise ConstraintError("Already finalized") + self.do_finalize(fragment, *args, **kwargs) + self.finalized = True + + def do_finalize(self, fragment, *args, **kwargs): + """overload this and e.g. add_platform_command()'s after the + modules had their say""" + pass + def add_source(self, filename, language=None): if language is None: language = tools.language_by_filename(filename) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index bb70fdd3c..2bc8c107f 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -150,6 +150,7 @@ class XilinxISEPlatform(GenericPlatform): def build(self, fragment, build_dir="build", build_name="top", ise_path="/opt/Xilinx", source=True, run=True): + self.finalize(fragment) tools.mkdir_noerror(build_dir) os.chdir(build_dir) From c1cf37f05a5f065fe4a6691691a4a5c6df3b6a0f Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 26 Jun 2013 20:49:07 -0600 Subject: [PATCH 61/83] add Avnet Spartan6 LX9 Micrboard platform --- mibuild/platforms/lx9_microboard.py | 115 ++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 mibuild/platforms/lx9_microboard.py diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py new file mode 100644 index 000000000..a4d13881f --- /dev/null +++ b/mibuild/platforms/lx9_microboard.py @@ -0,0 +1,115 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE + +_io = [ + ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"), + Misc("PULLDOWN"), Misc("TIG")), + + # TI CDCE913 programmable triple-output PLL + ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz + ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz + ("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz + + # Maxim DS1088LU oscillator, not populated + ("clk_backup", 0, Pins("R8"), IOStandard("LVCMOS33")), + + # TI CDCE913 PLL I2C control + ("pll", 0, + Subsignal("scl", Pins("P12")), + Subsignal("sda", Pins("U13")), + Misc("PULLUP"), + IOStandard("LVCMOS33")), + + # Micron N25Q128 SPI Flash + ("spiflash", 0, + Subsignal("clk", Pins("R15")), + Subsignal("cs_n", Pins("V3")), + Subsignal("dq", Pins("T13 R13 T14 V14")), + IOStandard("LVCMOS33")), + + ("user_dip", 0, Pins("B3 A3 B4 A4"), Misc("PULLDOWN"), + IOStandard("LVCMOS33")), + + ("user_led", 0, Pins("P4 L6 F5 C2"), Misc("SLEW=QUIETIO"), + IOStandard("LVCMOS18")), + + # PMOD extension connectors + ("pmod", 0, + Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")), + IOStandard("LVCMOS33")), + ("pmod", 1, + Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")), + IOStandard("LVCMOS33")), + + ("uart", 0, + Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("R7"), Misc("PULLUP")), + IOStandard("LVCMOS33")), + + ("ddram_clock", 0, + Subsignal("p", Pins("G3")), + Subsignal("n", Pins("G1")), + IOStandard("MOBILE_DDR")), # actually DIFF_ + + # Micron MT46H32M16LFBF-5 LPDDR + ("ddram", 0, + Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 " + "D2 D1 F4 D3 G6")), + Subsignal("ba", Pins("F2 F1")), + Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 " + "M3 M1 N2 N1 T2 T1 U2 U1")), + Subsignal("cke", Pins("H7")), + Subsignal("we_n", Pins("E3")), + Subsignal("cs_n", Pins("K6")), # NC! + Subsignal("cas_n", Pins("K5")), + Subsignal("ras_n", Pins("L5")), + Subsignal("dm", Pins("K3", "K4")), + Subsignal("dqs", Pins("L4", "P2")), + Subsignal("rzq", Pins("N4")), + IOStandard("MOBILE_DDR")), + + # Nat Semi DP83848J 10/100 Ethernet PHY + # pull-ups on rx_data set phy addr to 11110b + # and prevent isolate mode (addr 00000b) + ("eth_clocks", 0, + Subsignal("rx", Pins("L15")), + Subsignal("tx", Pins("H17")), + IOStandard("LVCMOS33")), + + ("eth", 0, + Subsignal("col", Pins("M18"), Misc("PULLDOWN")), + Subsignal("crs", Pins("N17"), Misc("PULLDOWN")), + Subsignal("mdc", Pins("M16")), + Subsignal("mdio", Pins("L18")), + Subsignal("rst_n", Pins("T18"), Misc("TIG")), + Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")), + Subsignal("dv", Pins("P17")), + Subsignal("rx_er", Pins("N18")), + Subsignal("tx_data", Pins("K18 K17 J18 J16")), + Subsignal("tx_en", Pins("L17")), + Subsignal("tx_er", Pins("L16")), # NC! + IOStandard("LVCMOS33")), + ] + + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io, + lambda p: CRG_SE(p, "clk_y3", "user_btn", 10.)) + self.add_platform_command(""" +CONFIG VCCAUX = "3.3"; +""") + + def do_finalize(self, fragment): + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_platform_command(""" +NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; +NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; +TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; +TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ContraintError: + pass From 7e4552bbfc839ddaea7161ed6f19a1bd2dec9445 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 27 Jun 2013 19:30:57 +0200 Subject: [PATCH 62/83] lx9_microboard: improve compat with other boards --- mibuild/platforms/lx9_microboard.py | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index a4d13881f..955aea528 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -5,6 +5,16 @@ _io = [ ("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"), Misc("PULLDOWN"), Misc("TIG")), + ("user_led", 0, Pins("P4"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + ("user_led", 1, Pins("L6"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + ("user_led", 2, Pins("F5"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + ("user_led", 3, Pins("C2"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")), + + ("user_dip", 0, Pins("B3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + ("user_dip", 1, Pins("A3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + ("user_dip", 2, Pins("B4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + ("user_dip", 3, Pins("A4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")), + # TI CDCE913 programmable triple-output PLL ("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz ("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz @@ -27,12 +37,6 @@ _io = [ Subsignal("dq", Pins("T13 R13 T14 V14")), IOStandard("LVCMOS33")), - ("user_dip", 0, Pins("B3 A3 B4 A4"), Misc("PULLDOWN"), - IOStandard("LVCMOS33")), - - ("user_led", 0, Pins("P4 L6 F5 C2"), Misc("SLEW=QUIETIO"), - IOStandard("LVCMOS18")), - # PMOD extension connectors ("pmod", 0, Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")), @@ -41,7 +45,7 @@ _io = [ Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")), IOStandard("LVCMOS33")), - ("uart", 0, + ("serial", 0, Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")), Subsignal("rx", Pins("R7"), Misc("PULLUP")), IOStandard("LVCMOS33")), From 1f3c941a7875013f62e741bcf6f5795b081cff4f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:22:59 +0200 Subject: [PATCH 63/83] platforms/m1: move generic platform commands to do_finalize --- mibuild/platforms/m1.py | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index ae391e768..80d61a149 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -120,3 +120,36 @@ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: CRG_SE(p, "clk50", "user_btn", 20.0)) + + def do_finalize(self, fragment): + try: + self.add_platform_command(""" +NET "{clk50}" TNM_NET = "GRPclk50"; +TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; +""", clk50=self.lookup_request("clk50")) + except ConstraintError: + pass + + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_platform_command(""" +NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; +NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; +TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; +TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ConstraintError: + pass + + for i in range(2): + si = "dviclk"+str(i) + try: + self.add_platform_command(""" +NET "{dviclk}" TNM_NET = "GRP"""+si+""""; +NET "{dviclk}" CLOCK_DEDICATED_ROUTE = FALSE; +TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%; +""", dviclk=self.lookup_request("dvi_in", i).clk) + except ConstraintError: + pass From 0784cd164f71425ada626006069a46be4252e1e4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:23:25 +0200 Subject: [PATCH 64/83] Add Mixxeo platform --- mibuild/platforms/mixxeo.py | 179 ++++++++++++++++++++++++++++++++++++ 1 file changed, 179 insertions(+) create mode 100644 mibuild/platforms/mixxeo.py diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py new file mode 100644 index 000000000..ebf87c3ca --- /dev/null +++ b/mibuild/platforms/mixxeo.py @@ -0,0 +1,179 @@ +from mibuild.generic_platform import * +from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE + +_io = [ + ("clk50", 0, Pins("AB13"), IOStandard("LVCMOS33")), + + # When executing softcore code in-place from the flash, we want + # the flash reset to be released before the system reset. + ("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)), + ("norflash", 0, + Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22", + "F21 K17 J17 E22 E20 H18 H19 F20", + "G19 C22 C20 D22 D21 F19 F18 D20 D19")), + Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7", + "AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")), + Subsignal("oe_n", Pins("M22")), + Subsignal("we_n", Pins("N20")), + Subsignal("ce_n", Pins("M21")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8) + ), + + ("serial", 0, + Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")), + Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")) + ), + + ("ddram_clock", 0, + Subsignal("p", Pins("M3")), + Subsignal("n", Pins("L4")), + IOStandard("SSTL2_I") + ), + ("ddram", 0, + Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")), + Subsignal("ba", Pins("A2 E6")), + Subsignal("cs_n", Pins("F7")), + Subsignal("cke", Pins("G7")), + Subsignal("ras_n", Pins("E5")), + Subsignal("cas_n", Pins("C4")), + Subsignal("we_n", Pins("D3")), + Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", + "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", + "M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")), + Subsignal("dm", Pins("E1 E3 F3 G4")), + Subsignal("dqs", Pins("F1 F2 H5 H6")), + IOStandard("SSTL2_I") + ), + + ("eth_clocks", 0, + Subsignal("phy", Pins("M20")), + Subsignal("rx", Pins("H22")), + Subsignal("tx", Pins("H21")), + IOStandard("LVCMOS33") + ), + ("eth", 0, + Subsignal("rst_n", Pins("R22")), + Subsignal("dv", Pins("V21")), + Subsignal("rx_er", Pins("V22")), + Subsignal("rx_data", Pins("U22 U20 T22 T21")), + Subsignal("tx_en", Pins("N19")), + Subsignal("tx_er", Pins("M19")), + Subsignal("tx_data", Pins("M16 L15 P19 P20")), + Subsignal("col", Pins("W20")), + Subsignal("crs", Pins("W22")), + IOStandard("LVCMOS33") + ), + + ("vga_clock", 0, Pins("A11"), IOStandard("LVCMOS33")), + ("vga", 0, + Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), + Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), + Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), + Subsignal("hsync_n", Pins("A14")), + Subsignal("vsync_n", Pins("C15")), + Subsignal("psave_n", Pins("B14")), + IOStandard("LVCMOS33") + ), + + ("mmc", 0, + Subsignal("clk", Pins("A10")), + Subsignal("cmd", Pins("B18")), + Subsignal("dat", Pins("A18 E16 C17 A17")), + IOStandard("LVCMOS33") + ), + + ("dvi_in", 0, + Subsignal("clk_p", Pins("K5"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("K4"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("H4"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("H3"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("K6"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("J6"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("K3"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("J4"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("U6"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("V5"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("AA8"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("Y6"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 1, + Subsignal("clk_p", Pins("J3"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("J1"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("M2"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("M1"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("L3"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("L1"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("K2"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("K1"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("T7"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("R7"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("AB9"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("Y5"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 2, + Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("W11"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("AA10"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("AB10"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("R11"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("T11"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("U9"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("AB7"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("AB8"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("V9"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 3, + Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("R19"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("P17"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("N16"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("M17"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("M18"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("AA14"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("AB17"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("T19"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("Y17"), IOStandard("LVCMOS33")) + ), +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io, + lambda p: CRG_SE(p, "clk50", None, 20.0)) + self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") + + def do_finalize(self, fragment): + try: + self.add_platform_command(""" +NET "{clk50}" TNM_NET = "GRPclk50"; +TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; +""", clk50=self.lookup_request("clk50")) + except ConstraintError: + pass + + try: + eth_clocks = self.lookup_request("eth_clocks") + self.add_platform_command(""" +NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; +NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; +TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; +TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; +TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; +""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) + except ConstraintError: + pass + + for i in range(4): + si = "dviclk"+str(i) + try: + self.add_platform_command(""" +NET "{dviclk}" TNM_NET = "GRP"""+si+""""; +TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%; +""", dviclk=self.lookup_request("dvi_in", i).clk_p) + except ConstraintError: + pass From 0883e99de3aad61fa98a73a5e61d9785ee5668e2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:25:29 +0200 Subject: [PATCH 65/83] Do not specify period constraints twice --- mibuild/platforms/m1.py | 2 +- mibuild/platforms/mixxeo.py | 2 +- mibuild/xilinx_ise.py | 7 ++++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 80d61a149..a096a38a2 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -119,7 +119,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: CRG_SE(p, "clk50", "user_btn", 20.0)) + lambda p: CRG_SE(p, "clk50", "user_btn")) def do_finalize(self, fragment): try: diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index ebf87c3ca..4ea764600 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -143,7 +143,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io, - lambda p: CRG_SE(p, "clk50", None, 20.0)) + lambda p: CRG_SE(p, "clk50", None)) self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") def do_finalize(self, fragment): diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 2bc8c107f..2ff3abec3 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -10,16 +10,17 @@ from mibuild.crg import SimpleCRG from mibuild import tools def _add_period_constraint(platform, clk, period): - platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk"; + if period is not None: + platform.add_platform_command("""NET "{clk}" TNM_NET = "GRPclk"; TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) class CRG_SE(SimpleCRG): - def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) _add_period_constraint(platform, self._clk, period) class CRG_DS(Module): - def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): + def __init__(self, platform, clk_name, rst_name, period=None, rst_invert=False): reset_less = rst_name is None self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) self._clk = platform.request(clk_name) From 71c2c5813b3c289e4ec306f3dff55bd25a602633 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:27:28 +0200 Subject: [PATCH 66/83] platforms/mixxeo: remove bank 3 DVI inputs --- mibuild/platforms/mixxeo.py | 32 ++------------------------------ 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 4ea764600..3dea2f603 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -83,34 +83,6 @@ _io = [ ), ("dvi_in", 0, - Subsignal("clk_p", Pins("K5"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("K4"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("H4"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("H3"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("K6"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("J6"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("K3"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("J4"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("U6"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("V5"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("AA8"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("Y6"), IOStandard("LVCMOS33")) - ), - ("dvi_in", 1, - Subsignal("clk_p", Pins("J3"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("J1"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("M2"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("M1"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("L3"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("L1"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("K2"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("K1"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("T7"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("R7"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("AB9"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("Y5"), IOStandard("LVCMOS33")) - ), - ("dvi_in", 2, Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")), @@ -124,7 +96,7 @@ _io = [ Subsignal("hpd_notif", Pins("AB8"), IOStandard("LVCMOS33")), Subsignal("hpd_en", Pins("V9"), IOStandard("LVCMOS33")) ), - ("dvi_in", 3, + ("dvi_in", 1, Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")), @@ -168,7 +140,7 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; except ConstraintError: pass - for i in range(4): + for i in range(2): si = "dviclk"+str(i) try: self.add_platform_command(""" From 05bc2885e98cdf9103a5c93736f054d2a334b938 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 19:49:39 +0200 Subject: [PATCH 67/83] Call finalize() after CRG creation --- mibuild/altera_quartus.py | 1 - mibuild/generic_platform.py | 2 ++ mibuild/xilinx_ise.py | 1 - 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index dbb336a75..4fc785509 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -74,7 +74,6 @@ quartus_sta {build_name}.qpf class AlteraQuartusPlatform(GenericPlatform): def build(self, fragment, build_dir="build", build_name="top", quartus_path="/opt/Altera", run=True): - self.finalize(fragment) tools.mkdir_noerror(build_dir) os.chdir(build_dir) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 2feb70e4d..86c12651e 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -209,6 +209,8 @@ class GenericPlatform: frag = fragment + crg.get_fragment() else: frag = fragment + # finalize + self.finalize(fragment) # generate Verilog src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, create_clock_domains=False, **kwargs) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 2ff3abec3..69306f5ae 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -151,7 +151,6 @@ class XilinxISEPlatform(GenericPlatform): def build(self, fragment, build_dir="build", build_name="top", ise_path="/opt/Xilinx", source=True, run=True): - self.finalize(fragment) tools.mkdir_noerror(build_dir) os.chdir(build_dir) From b18cffb5e8f37a0acb516da340817225d46a8bf8 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 4 Jul 2013 23:49:12 +0200 Subject: [PATCH 68/83] xilinx_ise: run tools like Project Navigator does to avoid weird bitgen behavior --- mibuild/xilinx_ise.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 69306f5ae..ad26c7520 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -108,10 +108,10 @@ def _run_ise(build_name, ise_path, source): build_script_contents += """ xst -ifn {build_name}.xst -ngdbuild -uc {build_name}.ucf {build_name}.ngc -map -ol high -w {build_name}.ngd -par -ol high -w {build_name}.ncd {build_name}-routed.ncd -bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}-routed.ncd {build_name}.bit +ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd +map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf +par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf +bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}.ncd {build_name}.bit """.format(build_name=build_name) build_script_file = "build_" + build_name + ".sh" tools.write_to_file(build_script_file, build_script_contents) From 78776b4bc9a68a3e2b31fb65f1f46d9ec53f8e9e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 21 Jul 2013 15:55:31 +0200 Subject: [PATCH 69/83] platforms/mixxeo: new pin assignments for 4 HDMI input ports --- mibuild/platforms/mixxeo.py | 40 +++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 3dea2f603..4caf66250 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -64,7 +64,7 @@ _io = [ IOStandard("LVCMOS33") ), - ("vga_clock", 0, Pins("A11"), IOStandard("LVCMOS33")), + ("vga_clock", 0, Pins("A10"), IOStandard("LVCMOS33")), ("vga", 0, Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), @@ -76,13 +76,41 @@ _io = [ ), ("mmc", 0, - Subsignal("clk", Pins("A10")), - Subsignal("cmd", Pins("B18")), - Subsignal("dat", Pins("A18 E16 C17 A17")), + Subsignal("clk", Pins("J3")), + Subsignal("cmd", Pins("L3")), + Subsignal("dat", Pins("L1 K2 M2 M1")), IOStandard("LVCMOS33") ), ("dvi_in", 0, + Subsignal("clk_p", Pins("K20"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("K19"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("B21"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("B22"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("A20"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A21"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("K16"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("J16"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("U6"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("V5"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("AA8"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("Y6"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 1, + Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("C17"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("A17"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("B18"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A18"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("T7"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("R7"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("AB9"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("Y5"), IOStandard("LVCMOS33")) + ), + ("dvi_in", 2, Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")), @@ -96,7 +124,7 @@ _io = [ Subsignal("hpd_notif", Pins("AB8"), IOStandard("LVCMOS33")), Subsignal("hpd_en", Pins("V9"), IOStandard("LVCMOS33")) ), - ("dvi_in", 1, + ("dvi_in", 3, Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")), @@ -140,7 +168,7 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; except ConstraintError: pass - for i in range(2): + for i in range(4): si = "dviclk"+str(i) try: self.add_platform_command(""" From f7f19b78e4d3168eda675eea1a484cec81f6511f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 26 Jul 2013 15:13:24 +0200 Subject: [PATCH 70/83] Fragment -> _Fragment --- mibuild/generic_platform.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 86c12651e..bfd6af73f 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -2,6 +2,7 @@ from copy import copy import os, argparse from migen.fhdl.std import * +from migen.fhdl.structure import _Fragment from migen.genlib.record import Record from migen.fhdl import verilog @@ -194,7 +195,7 @@ class GenericPlatform: self.add_source(os.path.join(root, filename), language) def get_verilog(self, fragment, **kwargs): - if not isinstance(fragment, Fragment): + if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() # We may create a temporary clock/reset generator that would request pins. # Save the constraint manager state so that such pin requests disappear From 702471aa3c06ac3dba4589ef86a154068dd8112b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 29 Jul 2013 12:24:49 +0200 Subject: [PATCH 71/83] platforms/mixxeo: new pin assignments to ease routing --- mibuild/platforms/mixxeo.py | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 4caf66250..bba399d09 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -77,8 +77,8 @@ _io = [ ("mmc", 0, Subsignal("clk", Pins("J3")), - Subsignal("cmd", Pins("L3")), - Subsignal("dat", Pins("L1 K2 M2 M1")), + Subsignal("cmd", Pins("K1")), + Subsignal("dat", Pins("J6 K6 N1 K5")), IOStandard("LVCMOS33") ), @@ -91,10 +91,10 @@ _io = [ Subsignal("data1_n", Pins("A21"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("K16"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("J16"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("U6"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("V5"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("AA8"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("Y6"), IOStandard("LVCMOS33")) + Subsignal("scl", Pins("G20"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("H16"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33")) ), ("dvi_in", 1, Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")), @@ -105,10 +105,10 @@ _io = [ Subsignal("data1_n", Pins("A18"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("T7"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("R7"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("AB9"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("Y5"), IOStandard("LVCMOS33")) + Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("F16"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33")) ), ("dvi_in", 2, Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")), @@ -119,10 +119,10 @@ _io = [ Subsignal("data1_n", Pins("AB10"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("R11"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("T11"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("U9"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("AB7"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("AB8"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("V9"), IOStandard("LVCMOS33")) + Subsignal("scl", Pins("C16"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("B16"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("D6"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("A4"), IOStandard("LVCMOS33")) ), ("dvi_in", 3, Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")), @@ -133,10 +133,10 @@ _io = [ Subsignal("data1_n", Pins("N16"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("M17"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("M18"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("AA14"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("AB17"), IOStandard("LVCMOS33")), - Subsignal("hpd_notif", Pins("T19"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("Y17"), IOStandard("LVCMOS33")) + Subsignal("scl", Pins("P21"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("N22"), IOStandard("LVCMOS33")), + Subsignal("hpd_notif", Pins("H17"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("C19"), IOStandard("LVCMOS33")) ), ] From 275a7ea94a24d0b277a40c2ae96d424879ad9c87 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 1 Aug 2013 17:46:09 +0200 Subject: [PATCH 72/83] Change license to BSD --- LICENSE | 705 ++--------------------------------- README | 2 - mibuild/altera_quartus.py | 2 +- mibuild/platforms/de0nano.py | 2 +- setup.py | 4 +- 5 files changed, 33 insertions(+), 682 deletions(-) diff --git a/LICENSE b/LICENSE index 443254047..cdc6303bf 100644 --- a/LICENSE +++ b/LICENSE @@ -1,676 +1,29 @@ - - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. - +Unless otherwise noted, Mibuild is copyright (C) 2013 Sebastien Bourdeauducq. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +Other authors retain ownership of their contributions. If a submission can +reasonably be considered independently copyrightable, it's yours and we +encourage you to claim it with appropriate copyright notices. This submission +then falls under the "otherwise noted" category. All submissions are strongly +encouraged to use the two-clause BSD license reproduced above. diff --git a/README b/README index d649b4b19..df95d062c 100644 --- a/README +++ b/README @@ -25,5 +25,3 @@ Mibuild is designed for Python 3.3. Send questions, comments and patches to devel [AT] lists.milkymist.org Description files for new boards welcome. We are also on IRC: #milkymist on the Freenode network. - -Mibuild is (c) 2013 Sebastien Bourdeauducq and GPLv3 (see LICENSE file). diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 4fc785509..72a6435ab 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -1,5 +1,5 @@ # This file is Copyright (c) 2013 Florent Kermarrec -# License: GPLv3 +# License: BSD import os, subprocess diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index 72a109d6b..567f87499 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -1,5 +1,5 @@ # This file is Copyright (c) 2013 Florent Kermarrec -# License: GPLv3 +# License: BSD from mibuild.generic_platform import * from mibuild.altera_quartus import AlteraQuartusPlatform, CRG_SE diff --git a/setup.py b/setup.py index 76cc0bc46..4322807b7 100755 --- a/setup.py +++ b/setup.py @@ -22,7 +22,7 @@ setup( url="http://www.milkymist.org", download_url="https://github.com/milkymist/mibuild", packages=find_packages(here), - license="GPL", + license="BSD", platforms=["Any"], keywords="HDL ASIC FPGA hardware design", classifiers=[ @@ -30,7 +30,7 @@ setup( "Environment :: Console", "Development Status :: Alpha", "Intended Audience :: Developers", - "License :: OSI Approved :: GNU General Public License (GPL)", + "License :: OSI Approved :: BSD License", "Operating System :: OS Independent", "Programming Language :: Python", ], From 6e64016885592b93c9a2eb00041a939c3f18ad97 Mon Sep 17 00:00:00 2001 From: Nina Engelhardt Date: Fri, 2 Aug 2013 17:10:33 +0200 Subject: [PATCH 73/83] add edif build routines --- mibuild/generic_platform.py | 34 ++++++++++++++++++++--------- mibuild/xilinx_ise.py | 43 ++++++++++++++++++++++++++----------- 2 files changed, 54 insertions(+), 23 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index bfd6af73f..62ddcf8f7 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -4,7 +4,7 @@ import os, argparse from migen.fhdl.std import * from migen.fhdl.structure import _Fragment from migen.genlib.record import Record -from migen.fhdl import verilog +from migen.fhdl import verilog, edif from mibuild import tools @@ -194,6 +194,18 @@ class GenericPlatform: if language is not None: self.add_source(os.path.join(root, filename), language) + def _resolve_signals(self, vns): + # resolve signal names in constraints + sc = self.constraint_manager.get_sig_constraints() + named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] + # resolve signal names in platform commands + pc = self.constraint_manager.get_platform_commands() + named_pc = [] + for template, args in pc: + name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items()) + named_pc.append(template.format(**name_dict)) + return named_sc, named_pc + def get_verilog(self, fragment, **kwargs): if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() @@ -215,19 +227,21 @@ class GenericPlatform: # generate Verilog src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, create_clock_domains=False, **kwargs) - # resolve signal names in constraints - sc = self.constraint_manager.get_sig_constraints() - named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] - # resolve signal names in platform commands - pc = self.constraint_manager.get_platform_commands() - named_pc = [] - for template, args in pc: - name_dict = dict((k, vns.get_name(sig)) for k, sig in args.items()) - named_pc.append(template.format(**name_dict)) + named_sc, named_pc = self._resolve_signals(vns) finally: self.constraint_manager.restore(backup) return src, named_sc, named_pc + def get_edif(self, fragment, cell_library, vendor, device, **kwargs): + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + # finalize + self.finalize(fragment) + # generate EDIF + src, vns = edif.convert(fragment, self.constraint_manager.get_io_signals(), cell_library, vendor, device, return_ns=True, **kwargs) + named_sc, named_pc = self._resolve_signals(vns) + return src, named_sc, named_pc + def build(self, fragment): raise NotImplementedError("GenericPlatform.build must be overloaded") diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index ad26c7520..b7dc25807 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -95,7 +95,7 @@ def _is_valid_version(path, v): except: return False -def _run_ise(build_name, ise_path, source): +def _run_ise(build_name, ise_path, source, mode="verilog"): if sys.platform == "win32" or sys.platform == "cygwin": source = False build_script_contents = "# Autogenerated by mibuild\nset -e\n" @@ -105,10 +105,15 @@ def _run_ise(build_name, ise_path, source): bits = struct.calcsize("P")*8 xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) build_script_contents += "source " + xilinx_settings_file + "\n" - - build_script_contents += """ + if mode == "edif": + build_script_contents += """ +ngdbuild -uc {build_name}.ucf {build_name}.edif {build_name}.ngd""".format(build_name=build_name) + else: + build_script_contents += """ xst -ifn {build_name}.xst -ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd +ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd""" + + build_script_contents += """ map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}.ncd {build_name}.bit @@ -149,19 +154,31 @@ class XilinxISEPlatform(GenericPlatform): so.update(special_overrides) return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs) + def get_edif(self, fragment, **kwargs): + return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs) + def build(self, fragment, build_dir="build", build_name="top", - ise_path="/opt/Xilinx", source=True, run=True): + ise_path="/opt/Xilinx", source=True, run=True, mode="verilog"): tools.mkdir_noerror(build_dir) os.chdir(build_dir) - v_src, named_sc, named_pc = self.get_verilog(fragment) - v_file = build_name + ".v" - tools.write_to_file(v_file, v_src) - sources = self.sources + [(v_file, "verilog")] - _build_files(self.device, sources, named_sc, named_pc, build_name) - if run: - _run_ise(build_name, ise_path, source) - + if mode == "verilog": + v_src, named_sc, named_pc = self.get_verilog(fragment) + v_file = build_name + ".v" + tools.write_to_file(v_file, v_src) + sources = self.sources + [(v_file, "verilog")] + _build_files(self.device, sources, named_sc, named_pc, build_name) + if run: + _run_ise(build_name, ise_path, source, mode="verilog") + + if mode == "edif": + e_src, named_sc, named_pc = self.get_edif(fragment) + e_file = build_name + ".edif" + tools.write_to_file(e_file, e_src) + sources = self.sources + [(e_file, "edif")] + tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) + if run: + _run_ise(build_name, ise_path, source, mode="edif") os.chdir("..") def build_arg_ns(self, ns, *args, **kwargs): From 9d531ba06a1d86edead693ef9db079b8c04a0286 Mon Sep 17 00:00:00 2001 From: user Date: Wed, 7 Aug 2013 18:26:40 +0200 Subject: [PATCH 74/83] Fix missing string replace. Added support for 32-bit ISE if 64-bit version is missing on 64-bit system. --- mibuild/xilinx_ise.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index b7dc25807..2ed130824 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -103,7 +103,11 @@ def _run_ise(build_name, ise_path, source, mode="verilog"): vers = [ver for ver in os.listdir(ise_path) if _is_valid_version(ise_path, ver)] tools_version = max(vers) bits = struct.calcsize("P")*8 - xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) + + xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) + if not os.path.exists(xilinx_settings_file) and bits == 64: + # if we are on 64-bit system but the toolchain isn't, try the 32-bit env. + xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, 32) build_script_contents += "source " + xilinx_settings_file + "\n" if mode == "edif": build_script_contents += """ @@ -111,7 +115,7 @@ ngdbuild -uc {build_name}.ucf {build_name}.edif {build_name}.ngd""".format(build else: build_script_contents += """ xst -ifn {build_name}.xst -ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd""" +ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd""".format(build_name=build_name) build_script_contents += """ map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf From 88611be3685671c1f9e8bc1456b9e8fc16c17007 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 8 Aug 2013 00:15:35 +0200 Subject: [PATCH 75/83] xilinx_ise: cleanup --- mibuild/xilinx_ise.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 2ed130824..31f6f65c8 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -104,24 +104,25 @@ def _run_ise(build_name, ise_path, source, mode="verilog"): tools_version = max(vers) bits = struct.calcsize("P")*8 - xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, bits) + xilinx_settings_file = os.path.join(ise_path, tools_version, "ISE_DS", "settings{0}.sh".format(bits)) if not os.path.exists(xilinx_settings_file) and bits == 64: # if we are on 64-bit system but the toolchain isn't, try the 32-bit env. - xilinx_settings_file = '%s/%s/ISE_DS/settings%d.sh' % (ise_path, tools_version, 32) + xilinx_settings_file = os.path.join(ise_path, tools_version, "ISE_DS", "settings32.sh") build_script_contents += "source " + xilinx_settings_file + "\n" if mode == "edif": build_script_contents += """ -ngdbuild -uc {build_name}.ucf {build_name}.edif {build_name}.ngd""".format(build_name=build_name) +ngdbuild -uc {build_name}.ucf {build_name}.edif {build_name}.ngd""" else: build_script_contents += """ xst -ifn {build_name}.xst -ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd""".format(build_name=build_name) +ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd""" build_script_contents += """ map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}.ncd {build_name}.bit -""".format(build_name=build_name) +""" + build_script_contents = build_script_contents.format(build_name=build_name) build_script_file = "build_" + build_name + ".sh" tools.write_to_file(build_script_file, build_script_contents) From 4ebbfa63bf0ef52be06a79a9d8f01af18dbb10d9 Mon Sep 17 00:00:00 2001 From: Nina Engelhardt Date: Sun, 11 Aug 2013 23:07:07 +0200 Subject: [PATCH 76/83] add mist synthesis mode to build --- mibuild/altera_quartus.py | 4 +++ mibuild/generic_platform.py | 54 ++++++++++++------------------------- mibuild/xilinx_ise.py | 12 ++++++++- 3 files changed, 32 insertions(+), 38 deletions(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 72a6435ab..0973545be 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -77,6 +77,10 @@ class AlteraQuartusPlatform(GenericPlatform): tools.mkdir_noerror(build_dir) os.chdir(build_dir) + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + self.finalize(fragment) + v_src, named_sc, named_pc = self.get_verilog(fragment) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 62ddcf8f7..17c8752a2 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -1,4 +1,3 @@ -from copy import copy import os, argparse from migen.fhdl.std import * @@ -138,11 +137,6 @@ class ConstraintManager: def get_platform_commands(self): return self.platform_commands - def save(self): - return copy(self.available), copy(self.matched), copy(self.platform_commands) - - def restore(self, backup): - self.available, self.matched, self.platform_commands = backup class GenericPlatform: def __init__(self, device, io, default_crg_factory=None, name=None): @@ -167,6 +161,12 @@ class GenericPlatform: def finalize(self, fragment, *args, **kwargs): if self.finalized: raise ConstraintError("Already finalized") + # if none exists, create a default clock domain and drive it + if not fragment.clock_domains: + if self.default_crg_factory is None: + raise NotImplementedError("No clock/reset generator defined by either platform or user") + crg = self.default_crg_factory(self) + fragment += crg.get_fragment() self.do_finalize(fragment, *args, **kwargs) self.finalized = True @@ -206,42 +206,22 @@ class GenericPlatform: named_pc.append(template.format(**name_dict)) return named_sc, named_pc - def get_verilog(self, fragment, **kwargs): + def _get_source(self, fragment, gen_fn): if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() - # We may create a temporary clock/reset generator that would request pins. - # Save the constraint manager state so that such pin requests disappear - # at the end of this function. - backup = self.constraint_manager.save() - try: - # if none exists, create a default clock domain and drive it - if not fragment.clock_domains: - if self.default_crg_factory is None: - raise NotImplementedError("No clock/reset generator defined by either platform or user") - crg = self.default_crg_factory(self) - frag = fragment + crg.get_fragment() - else: - frag = fragment - # finalize - self.finalize(fragment) - # generate Verilog - src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), - return_ns=True, create_clock_domains=False, **kwargs) - named_sc, named_pc = self._resolve_signals(vns) - finally: - self.constraint_manager.restore(backup) - return src, named_sc, named_pc - - def get_edif(self, fragment, cell_library, vendor, device, **kwargs): - if not isinstance(fragment, _Fragment): - fragment = fragment.get_fragment() - # finalize - self.finalize(fragment) - # generate EDIF - src, vns = edif.convert(fragment, self.constraint_manager.get_io_signals(), cell_library, vendor, device, return_ns=True, **kwargs) + # generate source + src, vns = gen_fn(fragment) named_sc, named_pc = self._resolve_signals(vns) return src, named_sc, named_pc + def get_verilog(self, fragment, **kwargs): + return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(), + return_ns=True, create_clock_domains=False, **kwargs)) + + def get_edif(self, fragment, cell_library, vendor, device, **kwargs): + return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(), + cell_library, vendor, device, return_ns=True, **kwargs)) + def build(self, fragment): raise NotImplementedError("GenericPlatform.build must be overloaded") diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 31f6f65c8..8df2cfba2 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -4,6 +4,7 @@ from decimal import Decimal from migen.fhdl.std import * from migen.fhdl.specials import SynthesisDirective from migen.genlib.cdc import * +from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * from mibuild.crg import SimpleCRG @@ -167,6 +168,10 @@ class XilinxISEPlatform(GenericPlatform): tools.mkdir_noerror(build_dir) os.chdir(build_dir) + if not isinstance(fragment, _Fragment): + fragment = fragment.get_fragment() + self.finalize(fragment) + if mode == "verilog": v_src, named_sc, named_pc = self.get_verilog(fragment) v_file = build_name + ".v" @@ -176,7 +181,11 @@ class XilinxISEPlatform(GenericPlatform): if run: _run_ise(build_name, ise_path, source, mode="verilog") - if mode == "edif": + if mode == "mist": + from mist import synthesize + synthesize(fragment, self.constraint_manager.get_io_signals()) + + if mode == "edif" or mode == "mist": e_src, named_sc, named_pc = self.get_edif(fragment) e_file = build_name + ".edif" tools.write_to_file(e_file, e_src) @@ -184,6 +193,7 @@ class XilinxISEPlatform(GenericPlatform): tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) if run: _run_ise(build_name, ise_path, source, mode="edif") + os.chdir("..") def build_arg_ns(self, ns, *args, **kwargs): From 316faa7fa88fe6add69addaf680726646496949f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 14 Aug 2013 00:46:30 +0200 Subject: [PATCH 77/83] platforms/m1: resetless by default --- mibuild/platforms/m1.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index a096a38a2..d72a6bde1 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -119,7 +119,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: CRG_SE(p, "clk50", "user_btn")) + lambda p: CRG_SE(p, "clk50", None)) def do_finalize(self, fragment): try: From 9569152309e2032b71f1712db9046741166dfce3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 26 Aug 2013 18:08:01 +0200 Subject: [PATCH 78/83] altera_quartus: fix import _Fragment --- mibuild/altera_quartus.py | 1 + 1 file changed, 1 insertion(+) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 0973545be..781b104ff 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -3,6 +3,7 @@ import os, subprocess +from migen.fhdl.structure import _Fragment from mibuild.generic_platform import * from mibuild.crg import SimpleCRG from mibuild import tools From d57344b8ae2861804aa0b430247d42dd69853ddf Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 6 Sep 2013 23:10:01 +0200 Subject: [PATCH 79/83] platforms/mixxeo: add LED --- mibuild/platforms/mixxeo.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index bba399d09..cfd1d144c 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -2,6 +2,8 @@ from mibuild.generic_platform import * from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE _io = [ + ("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")), + ("clk50", 0, Pins("AB13"), IOStandard("LVCMOS33")), # When executing softcore code in-place from the flash, we want From ebe8a27de9592a69656b946c5fc94335ac59227a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 14 Sep 2013 19:36:02 +0200 Subject: [PATCH 80/83] mixxeo: swap pairs 0 and 1 on DVI1 --- mibuild/platforms/mixxeo.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index cfd1d144c..1eb5d83e2 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -101,10 +101,10 @@ _io = [ ("dvi_in", 1, Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("C17"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("A17"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("B18"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("A18"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("B18"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("A18"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("C17"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("A17"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")), Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")), From df7ca037cbee47ce76024796b3f1cf96bea124bc Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 16 Sep 2013 19:17:00 +0200 Subject: [PATCH 81/83] mixxeo: use -2 speed grade --- mibuild/platforms/mixxeo.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index cfd1d144c..52318d7f8 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -144,7 +144,7 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): - XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-3", _io, + XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: CRG_SE(p, "clk50", None)) self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") From 140ddd31a415cdbc3a5c7c5cc8705105cbc98820 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 17 Sep 2013 18:14:41 +0200 Subject: [PATCH 82/83] mixxeo: add DVI output pins --- mibuild/platforms/mixxeo.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index 2285c0981..c797b09e7 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -66,8 +66,8 @@ _io = [ IOStandard("LVCMOS33") ), - ("vga_clock", 0, Pins("A10"), IOStandard("LVCMOS33")), - ("vga", 0, + ("vga_out", 0, + Subsignal("clk", Pins("A10")), Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")), Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")), Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")), @@ -76,6 +76,16 @@ _io = [ Subsignal("psave_n", Pins("B14")), IOStandard("LVCMOS33") ), + ("dvi_out", 0, + Subsignal("clk_p", Pins("W12"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("Y12"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("Y16"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("W15"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("AA16"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("AB16"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("Y15"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("AB15"), IOStandard("TMDS_33")), + ), ("mmc", 0, Subsignal("clk", Pins("J3")), From 9d5931c969810a236de2a2713cfd5e509839d097 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 19 Nov 2013 23:15:42 +0100 Subject: [PATCH 83/83] platforms/mixxeo: update DVI input timing constraints --- mibuild/platforms/mixxeo.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index c797b09e7..12b242fb8 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -185,7 +185,7 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; try: self.add_platform_command(""" NET "{dviclk}" TNM_NET = "GRP"""+si+""""; -TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 26.7 ns HIGH 50%; +TIMESPEC "TS"""+si+"""" = PERIOD "GRP"""+si+"""" 12.00 ns HIGH 50%; """, dviclk=self.lookup_request("dvi_in", i).clk_p) except ConstraintError: pass