From 62f70a54f0fdcc948ff88cbf0c83890dcdede527 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 8 Dec 2011 21:19:40 +0100 Subject: [PATCH] corelogic: MC divider module --- migen/corelogic/divider.py | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 migen/corelogic/divider.py diff --git a/migen/corelogic/divider.py b/migen/corelogic/divider.py new file mode 100644 index 000000000..e19ffc2bf --- /dev/null +++ b/migen/corelogic/divider.py @@ -0,0 +1,43 @@ +from migen.fhdl import structure as f + +class Inst: + def __init__(self, w): + self.w = w + + d = partial(f.Declare, self) + + d("start_i") + d("dividend_i", f.BV(w)) + d("divisor_i", f.BV(w)) + d("ready_o") + d("quotient_o", f.BV(w)) + d("remainder_o", f.BV(w)) + + d("_qr", f.BV(2*w)) + d("_counter", f.BV(f.BitsFor(w))) + d("_divisor_r", f.BV(w)) + d("_diff", f.BV(w+1)) + + def GetFragment(self): + a = f.Assign + comb = [ + a(self.quotient_o, self._qr[:self.w]), + a(self.remainder_o, self._qr[self.w:]), + a(self.ready_o, self._counter == f.Constant(0, self._counter.bv)), + a(self._diff, self.remainder_o - self._divisor_r) + ] + sync = [ + f.If(self.start_i == 1, [ + a(self._counter, self.w), + a(self._qr, self.dividend_i), + a(self._divisor_r, self.divisor_i) + ], [ + f.If(self.ready_o == 0, [ + f.If(self._diff[self.w] == 1, + [a(self._qr, f.Cat(0, self._qr[:2*self.w-1]))], + [a(self._qr, f.Cat(1, self._qr[:self.w-1], self._diff[:self.w]))]), + a(self._counter, self._counter - f.Constant(1, self._counter.bv)), + ]) + ]) + ] + return f.Fragment(comb, sync) \ No newline at end of file