From 6367fc6cabc58e35a9bee3f21163772f43baf1a7 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Fri, 9 Sep 2022 13:19:36 +0200 Subject: [PATCH] update naxriscv comments --- litex/soc/cores/cpu/naxriscv/core.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 234e5784e..ece699037 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -471,11 +471,11 @@ class NaxRiscv(CPU): # Generate memory map from CPU perspective # naxriscv modes: - # r,w : regular memory load/store - # i,o : peripheral memory load/store - # x : instruction fetchable (execute) - # litex modes: - # rwx : load, store, execute (everything is peripheral per default) + # r,w,x,c : readable, writeable, executable, caching allowed + # io : IO region (Implies P bus, preserve memory order, no dcache) + # naxriscv bus: + # p : peripheral + # m : memory NaxRiscv.memory_regions = [] for name, region in self.soc.bus.io_regions.items(): NaxRiscv.memory_regions.append( (region.origin, region.size, "io", "p") ) # IO is only allowed on the p bus