From 63b879797841ae6a7d9accd8f40bdc3681900b62 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 May 2015 12:55:51 +0200
Subject: [PATCH] liteeth: move mac to core

---
 misoclib/com/liteeth/core/__init__.py                    | 2 +-
 misoclib/com/liteeth/{ => core}/mac/__init__.py          | 6 +++---
 misoclib/com/liteeth/{ => core}/mac/common.py            | 0
 misoclib/com/liteeth/{ => core}/mac/core/__init__.py     | 2 +-
 misoclib/com/liteeth/{ => core}/mac/core/crc.py          | 0
 misoclib/com/liteeth/{ => core}/mac/core/gap.py          | 0
 misoclib/com/liteeth/{ => core}/mac/core/last_be.py      | 0
 misoclib/com/liteeth/{ => core}/mac/core/padding.py      | 0
 misoclib/com/liteeth/{ => core}/mac/core/preamble.py     | 0
 misoclib/com/liteeth/{ => core}/mac/frontend/__init__.py | 0
 misoclib/com/liteeth/{ => core}/mac/frontend/sram.py     | 0
 misoclib/com/liteeth/{ => core}/mac/frontend/wishbone.py | 2 +-
 misoclib/com/liteeth/test/arp_tb.py                      | 2 +-
 misoclib/com/liteeth/test/mac_core_tb.py                 | 2 +-
 misoclib/com/liteeth/test/mac_wishbone_tb.py             | 2 +-
 targets/kc705.py                                         | 2 +-
 targets/mlabs_video.py                                   | 2 +-
 targets/simple.py                                        | 2 +-
 18 files changed, 12 insertions(+), 12 deletions(-)
 rename misoclib/com/liteeth/{ => core}/mac/__init__.py (87%)
 rename misoclib/com/liteeth/{ => core}/mac/common.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/core/__init__.py (97%)
 rename misoclib/com/liteeth/{ => core}/mac/core/crc.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/core/gap.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/core/last_be.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/core/padding.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/core/preamble.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/frontend/__init__.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/frontend/sram.py (100%)
 rename misoclib/com/liteeth/{ => core}/mac/frontend/wishbone.py (96%)

diff --git a/misoclib/com/liteeth/core/__init__.py b/misoclib/com/liteeth/core/__init__.py
index f789ac7e5..d099485f3 100644
--- a/misoclib/com/liteeth/core/__init__.py
+++ b/misoclib/com/liteeth/core/__init__.py
@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 from misoclib.com.liteeth.core.arp import LiteEthARP
 from misoclib.com.liteeth.core.ip import LiteEthIP
 from misoclib.com.liteeth.core.udp import LiteEthUDP
diff --git a/misoclib/com/liteeth/mac/__init__.py b/misoclib/com/liteeth/core/mac/__init__.py
similarity index 87%
rename from misoclib/com/liteeth/mac/__init__.py
rename to misoclib/com/liteeth/core/mac/__init__.py
index 5c2a06752..14bbf74b5 100644
--- a/misoclib/com/liteeth/mac/__init__.py
+++ b/misoclib/com/liteeth/core/mac/__init__.py
@@ -1,7 +1,7 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.common import *
-from misoclib.com.liteeth.mac.core import LiteEthMACCore
-from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from misoclib.com.liteeth.core.mac.common import *
+from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
+from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):
diff --git a/misoclib/com/liteeth/mac/common.py b/misoclib/com/liteeth/core/mac/common.py
similarity index 100%
rename from misoclib/com/liteeth/mac/common.py
rename to misoclib/com/liteeth/core/mac/common.py
diff --git a/misoclib/com/liteeth/mac/core/__init__.py b/misoclib/com/liteeth/core/mac/core/__init__.py
similarity index 97%
rename from misoclib/com/liteeth/mac/core/__init__.py
rename to misoclib/com/liteeth/core/mac/core/__init__.py
index f8b18f739..f31cafa21 100644
--- a/misoclib/com/liteeth/mac/core/__init__.py
+++ b/misoclib/com/liteeth/core/mac/core/__init__.py
@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
+from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
 from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
 
 
diff --git a/misoclib/com/liteeth/mac/core/crc.py b/misoclib/com/liteeth/core/mac/core/crc.py
similarity index 100%
rename from misoclib/com/liteeth/mac/core/crc.py
rename to misoclib/com/liteeth/core/mac/core/crc.py
diff --git a/misoclib/com/liteeth/mac/core/gap.py b/misoclib/com/liteeth/core/mac/core/gap.py
similarity index 100%
rename from misoclib/com/liteeth/mac/core/gap.py
rename to misoclib/com/liteeth/core/mac/core/gap.py
diff --git a/misoclib/com/liteeth/mac/core/last_be.py b/misoclib/com/liteeth/core/mac/core/last_be.py
similarity index 100%
rename from misoclib/com/liteeth/mac/core/last_be.py
rename to misoclib/com/liteeth/core/mac/core/last_be.py
diff --git a/misoclib/com/liteeth/mac/core/padding.py b/misoclib/com/liteeth/core/mac/core/padding.py
similarity index 100%
rename from misoclib/com/liteeth/mac/core/padding.py
rename to misoclib/com/liteeth/core/mac/core/padding.py
diff --git a/misoclib/com/liteeth/mac/core/preamble.py b/misoclib/com/liteeth/core/mac/core/preamble.py
similarity index 100%
rename from misoclib/com/liteeth/mac/core/preamble.py
rename to misoclib/com/liteeth/core/mac/core/preamble.py
diff --git a/misoclib/com/liteeth/mac/frontend/__init__.py b/misoclib/com/liteeth/core/mac/frontend/__init__.py
similarity index 100%
rename from misoclib/com/liteeth/mac/frontend/__init__.py
rename to misoclib/com/liteeth/core/mac/frontend/__init__.py
diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/core/mac/frontend/sram.py
similarity index 100%
rename from misoclib/com/liteeth/mac/frontend/sram.py
rename to misoclib/com/liteeth/core/mac/frontend/sram.py
diff --git a/misoclib/com/liteeth/mac/frontend/wishbone.py b/misoclib/com/liteeth/core/mac/frontend/wishbone.py
similarity index 96%
rename from misoclib/com/liteeth/mac/frontend/wishbone.py
rename to misoclib/com/liteeth/core/mac/frontend/wishbone.py
index 91c227f14..48a8f1d24 100644
--- a/misoclib/com/liteeth/mac/frontend/wishbone.py
+++ b/misoclib/com/liteeth/core/mac/frontend/wishbone.py
@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.frontend import sram
+from misoclib.com.liteeth.core.mac.frontend import sram
 
 from migen.bus import wishbone
 from migen.fhdl.simplify import FullMemoryWE
diff --git a/misoclib/com/liteeth/test/arp_tb.py b/misoclib/com/liteeth/test/arp_tb.py
index f4b1fee48..085645020 100644
--- a/misoclib/com/liteeth/test/arp_tb.py
+++ b/misoclib/com/liteeth/test/arp_tb.py
@@ -4,7 +4,7 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 from misoclib.com.liteeth.core.arp import LiteEthARP
 
 from misoclib.com.liteeth.test.common import *
diff --git a/misoclib/com/liteeth/test/mac_core_tb.py b/misoclib/com/liteeth/test/mac_core_tb.py
index c852417d3..c7afdc296 100644
--- a/misoclib/com/liteeth/test/mac_core_tb.py
+++ b/misoclib/com/liteeth/test/mac_core_tb.py
@@ -4,7 +4,7 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.core import LiteEthMACCore
+from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
 
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac
diff --git a/misoclib/com/liteeth/test/mac_wishbone_tb.py b/misoclib/com/liteeth/test/mac_wishbone_tb.py
index cfc1efdc7..19e7b66d6 100644
--- a/misoclib/com/liteeth/test/mac_wishbone_tb.py
+++ b/misoclib/com/liteeth/test/mac_wishbone_tb.py
@@ -4,7 +4,7 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac
diff --git a/targets/kc705.py b/targets/kc705.py
index 4cd792d66..8f65fa911 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -9,7 +9,7 @@ from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
 
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class _CRG(Module):
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index 69ea8e7cc..9e5eaf1b0 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -15,7 +15,7 @@ from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
 from misoclib.com import gpio
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class _MXClockPads:
diff --git a/targets/simple.py b/targets/simple.py
index 62ea87ce3..89bd57e2b 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -4,7 +4,7 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC, mem_decoder
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class BaseSoC(SoC):