From 653b74fe98022f87abe62ad637d4596052f42617 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 21 Feb 2023 08:26:21 +0100
Subject: [PATCH] gen/fhdl/module: Fix typo.

---
 litex/gen/fhdl/module.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/gen/fhdl/module.py b/litex/gen/fhdl/module.py
index 0ddb24699..a3fa016b1 100644
--- a/litex/gen/fhdl/module.py
+++ b/litex/gen/fhdl/module.py
@@ -40,7 +40,7 @@ class LiteXModule(Module, AutoCSR, AutoDoc):
             print(other)
             m.submodules += other
         # - m += special_x  equivalent of Migen's m.specials += special_x.
-        elif isinstnace(other, Special):
+        elif isinstance(other, Special):
             m.specials += other
         # - m += cd_x  equivalent of Migen's m.clock_domains += cd_x.
         elif isinstance(other, ClockDomain):