From 65babd65009cddc59f4285f8105aea886c7b6ef0 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Mon, 28 Jun 2021 11:50:45 +0200 Subject: [PATCH] soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite --- litex/soc/interconnect/axi.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 414248c9d..3be196715 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -92,10 +92,10 @@ def connect_to_pads(bus, pads, mode="master", axi_full=False): } for channel, mode in channel_modes.items(): ch = getattr(bus, channel) - for name, width in ( - [("valid", 1)] + - [("last", 1)] if (ch in ["w", "r"] and axi_full) else [] + - ch.description.payload_layout): + sig_list = [("valid", 1)] + ch.description.payload_layout + if ch in ["w", "r"] and axi_full: + sig_list += [("last", 1)] + for name, width in sig_list: sig = getattr(ch, name) pad = getattr(pads, channel + name) if mode == "master":