From bffd59726c9de1bc1bdcb9b9048f33f4eb87c260 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Wed, 20 Jul 2022 02:43:02 +0200 Subject: [PATCH 1/2] test/axi_lite: rename a test for clarity; parametrize address and data width; add another test call with 64b data width --- test/test_axi_lite.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/test/test_axi_lite.py b/test/test_axi_lite.py index 08e106302..27fe57fff 100644 --- a/test/test_axi_lite.py +++ b/test/test_axi_lite.py @@ -146,18 +146,19 @@ class AXILitePatternGenerator: # TestAXILite -------------------------------------------------------------------------------------- class TestAXILite(unittest.TestCase): - def test_wishbone2axi2wishbone(self): + def test_wishbone2axilite2wishbone(self, data_width=32, address_width=32): class DUT(Module): def __init__(self): - self.wishbone = wishbone.Interface(data_width=32, adr_width=30) + self.wishbone = wishbone.Interface(data_width=data_width, + adr_width=address_width - log2_int(data_width // 8)) # # # - axi = AXILiteInterface(data_width=32, address_width=32) - wb = wishbone.Interface(data_width=32, adr_width=30) + axi_lite = AXILiteInterface(data_width=data_width, address_width=address_width) + wb = wishbone.Interface(data_width=data_width, adr_width=address_width - log2_int(data_width // 8)) - wishbone2axi = Wishbone2AXILite(self.wishbone, axi) - axi2wishbone = AXILite2Wishbone(axi, wb) + wishbone2axi = Wishbone2AXILite(self.wishbone, axi_lite) + axi2wishbone = AXILite2Wishbone(axi_lite, wb) self.submodules += wishbone2axi, axi2wishbone sram = wishbone.SRAM(1024, init=[0x12345678, 0xa55aa55a]) @@ -180,6 +181,9 @@ class TestAXILite(unittest.TestCase): run_simulation(dut, [generator(dut)]) self.assertEqual(dut.errors, 0) + def test_wishbone2axilite2wishbone_dw64(self): + return self.test_wishbone2axilite2wishbone(data_width=64) + def test_axilite2axi2mem(self): class DUT(Module): def __init__(self, mem_bus="wishbone"): From 65d5161408d80d6aca80031d67c722eb7dca9f88 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Wed, 20 Jul 2022 02:44:57 +0200 Subject: [PATCH 2/2] test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width --- test/test_axi_lite.py | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/test/test_axi_lite.py b/test/test_axi_lite.py index 27fe57fff..49548d055 100644 --- a/test/test_axi_lite.py +++ b/test/test_axi_lite.py @@ -184,12 +184,12 @@ class TestAXILite(unittest.TestCase): def test_wishbone2axilite2wishbone_dw64(self): return self.test_wishbone2axilite2wishbone(data_width=64) - def test_axilite2axi2mem(self): + def test_axilite2axi2mem(self, data_width=32, address_width=32): class DUT(Module): def __init__(self, mem_bus="wishbone"): - self.axi_lite = AXILiteInterface() + self.axi_lite = AXILiteInterface(data_width=data_width, address_width=address_width) - axi = AXIInterface() + axi = AXIInterface(data_width=data_width, address_width=address_width) self.submodules.axil2axi = AXILite2AXI(self.axi_lite, axi) interface_cls, converter_cls, sram_cls = { @@ -197,25 +197,27 @@ class TestAXILite(unittest.TestCase): "axi_lite": (AXILiteInterface, AXI2AXILite, AXILiteSRAM), }[mem_bus] - bus_kwargs = {"adr_width" : 30} if mem_bus == "wishbone" else {} + bus_kwargs = {"data_width": data_width} + if mem_bus == "wishbone": + bus_kwargs["adr_width"] = address_width - log2_int(data_width // 8) bus = interface_cls(**bus_kwargs) self.submodules += converter_cls(axi, bus) - sram = sram_cls(1024, init=[0x12345678, 0xa55aa55a]) + sram = sram_cls(1024, init=[0x12345678, 0xa55aa55a], bus=bus) self.submodules += sram - self.comb += bus.connect(sram.bus) def generator(axi_lite, datas, resps): + dw_bytes = data_width // 8 data, resp = (yield from axi_lite.read(0x00)) resps.append((resp, RESP_OKAY)) datas.append((data, 0x12345678)) - data, resp = (yield from axi_lite.read(0x04)) + data, resp = (yield from axi_lite.read(dw_bytes * 1)) resps.append((resp, RESP_OKAY)) datas.append((data, 0xa55aa55a)) for i in range(32): - resp = (yield from axi_lite.write(4*i, i)) + resp = (yield from axi_lite.write(dw_bytes * i, i)) resps.append((resp, RESP_OKAY)) for i in range(32): - data, resp = (yield from axi_lite.read(4*i)) + data, resp = (yield from axi_lite.read(dw_bytes * i)) resps.append((resp, RESP_OKAY)) datas.append((data, i)) @@ -234,6 +236,9 @@ class TestAXILite(unittest.TestCase): msg = "\n".join("0x{:08x} vs 0x{:08x}".format(actual, expected) for actual, expected in datas) self.assertEqual(*actual_expected(datas), msg="actual vs expected:\n" + msg) + def test_axilite2axi2mem_dw64(self): + return self.test_axilite2axi2mem(data_width=64) + def test_axilite2csr(self): @passive def csr_mem_handler(csr, mem):