diff --git a/CHANGES.md b/CHANGES.md
index 74346a571..8b552109b 100644
--- a/CHANGES.md
+++ b/CHANGES.md
@@ -12,6 +12,7 @@
 	- liteeth/core/icmp   : Fixed length check on LiteEthICMPEcho before passing data to buffer.
 	- LiteXModule/CSR     : Fixed CSR collection order causing CSR clock domain to be changed.
 	- litepcie/US(P)      : Fixed root cause of possible MSI deadlock.
+	- soc/add_uart        : Fixed stub behavior (sink/source swap).
 
 	[> Added
 	--------
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 60b95fa30..f87106496 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1394,7 +1394,7 @@ class LiteXSoC(SoC):
         # Stub / Stream.
         elif uart_name in ["stub", "stream"]:
             uart = UART(tx_fifo_depth=0, rx_fifo_depth=0)
-            self.comb += uart.sink.ready.eq(uart_name == "stub")
+            self.comb += uart.source.ready.eq(uart_name == "stub")
 
         # UARTBone.
         elif uart_name in ["uartbone"]: