From 66b4bae7c8c9c6442a1265566c5efc26e8652da8 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 8 May 2013 22:31:42 +0200
Subject: [PATCH] top: connect dvisampler DMA IRQs

---
 top.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/top.py b/top.py
index f3ed0b94d..604cd6fef 100644
--- a/top.py
+++ b/top.py
@@ -83,6 +83,8 @@ class SoC(Module):
 		"uart":			0,
 		"timer0":		1,
 		"minimac":		2,
+		"dvisampler0":  3,
+		"dvisampler1":  4,
 	}
 
 	def __init__(self, platform):
@@ -153,7 +155,8 @@ class SoC(Module):
 		# Interrupts
 		#
 		for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
-			self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
+			if hasattr(self, k):
+				self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
 
 		#
 		# Clocking