From 66ce40d880826e1a17f88e97791796ef8777ef78 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 10:48:59 +0200 Subject: [PATCH] liteeth: pep8 (E222) --- misoclib/com/liteeth/core/etherbone/record.py | 4 ++-- misoclib/com/liteeth/example_designs/make.py | 2 +- misoclib/com/liteeth/generic/depacketizer.py | 2 +- misoclib/com/liteeth/mac/core/__init__.py | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/misoclib/com/liteeth/core/etherbone/record.py b/misoclib/com/liteeth/core/etherbone/record.py index 09f9b1985..90d98a50e 100644 --- a/misoclib/com/liteeth/core/etherbone/record.py +++ b/misoclib/com/liteeth/core/etherbone/record.py @@ -152,7 +152,7 @@ class LiteEthEtherboneRecord(Module): # receive record, decode it and generate mmap stream self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer() - self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver() + self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver() self.comb += [ Record.connect(sink, depacketizer.sink), Record.connect(depacketizer.source, receiver.sink) @@ -169,7 +169,7 @@ class LiteEthEtherboneRecord(Module): ] # receive mmap stream, encode it and send records - self.submodules.sender = sender = LiteEthEtherboneRecordSender() + self.submodules.sender = sender = LiteEthEtherboneRecordSender() self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer() self.comb += [ Record.connect(sender.source, packetizer.sink), diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py index caf6a293b..a297da5bf 100644 --- a/misoclib/com/liteeth/example_designs/make.py +++ b/misoclib/com/liteeth/example_designs/make.py @@ -75,7 +75,7 @@ if __name__ == "__main__": platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) platform = platform_module.Platform(**platform_kwargs) - build_name = top_class.__name__.lower() + "-" + platform_name + build_name = top_class.__name__.lower() + "-" + platform_name top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() diff --git a/misoclib/com/liteeth/generic/depacketizer.py b/misoclib/com/liteeth/generic/depacketizer.py index c6e13dffa..49d1cf80e 100644 --- a/misoclib/com/liteeth/generic/depacketizer.py +++ b/misoclib/com/liteeth/generic/depacketizer.py @@ -80,7 +80,7 @@ class LiteEthDepacketizer(Module): fsm.act("COPY", sink.ack.eq(source.ack), source.stb.eq(sink.stb | no_payload), - If(source.stb & source.ack & source.eop, + If(source.stb & source.ack & source.eop, NextState("IDLE") ) ) diff --git a/misoclib/com/liteeth/mac/core/__init__.py b/misoclib/com/liteeth/mac/core/__init__.py index da512aeec..127d645d8 100644 --- a/misoclib/com/liteeth/mac/core/__init__.py +++ b/misoclib/com/liteeth/mac/core/__init__.py @@ -79,8 +79,8 @@ class LiteEthMACCore(Module, AutoCSR): # Cross Domain Crossing tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) - self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) - self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) + self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) + self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) tx_pipeline += [tx_cdc] rx_pipeline += [rx_cdc]