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pytholite/compiler: support bitslice
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37f113c3ea
commit
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1 changed files with 15 additions and 5 deletions
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@ -3,6 +3,7 @@ import ast
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from operator import itemgetter
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Slice
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from migen.fhdl import visit as fhdl
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from migen.corelogic.fsm import FSM
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from migen.pytholite import transel
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@ -186,12 +187,12 @@ class _Compiler:
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raise NotImplementedError
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# expressions
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def visit_expr(self, node, allow_call=False):
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def visit_expr(self, node, allow_registers=False):
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if isinstance(node, ast.Call):
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if allow_call:
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return self.visit_expr_call(node)
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else:
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r = self.visit_expr_call(node)
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if not allow_registers and isinstance(r, _Register):
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raise NotImplementedError
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return r
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elif isinstance(node, ast.BinOp):
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return self.visit_expr_binop(node)
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elif isinstance(node, ast.Compare):
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@ -213,6 +214,16 @@ class _Compiler:
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raise TypeError("Register() takes exactly 1 argument")
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nbits = ast.literal_eval(node.args[0])
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return _Register(self.targetname, nbits)
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elif callee == transel.bitslice:
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if len(node.args) != 2 and len(node.args) != 3:
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raise TypeError("bitslice() takes 2 or 3 arguments")
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val = self.visit_expr(node.args[0])
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low = ast.literal_eval(node.args[1])
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if len(node.args) == 3:
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up = ast.literal_eval(node.args[2])
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else:
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up = low + 1
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return _Slice(val, low, up)
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else:
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raise NotImplementedError
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@ -324,4 +335,3 @@ def make_pytholite(func):
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fsmf = _LowerAbstractLoad().visit(fsm.get_fragment())
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return regf + fsmf
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