diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 5e88646bd..1517b7bd0 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -23,7 +23,7 @@ class LiteEthMAC(Module, AutoCSR):
 			self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
 			self.comb += Port.connect(self.interface, self.core)
 			self.ev, self.bus = self.interface.sram.ev, self.interface.bus
-			self.csrs = self.interface.get_csrs()
+			self.csrs = self.interface.get_csrs() + self.core.get_csrs()
 		elif interface == "dma":
 			raise NotImplementedError
 		else: