From 67958f74484e18caa69ddd862158e1fad1f77f34 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Feb 2015 14:44:36 +0100 Subject: [PATCH] mac: fix missing core csr generation --- liteeth/mac/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py index 5e88646bd..1517b7bd0 100644 --- a/liteeth/mac/__init__.py +++ b/liteeth/mac/__init__.py @@ -23,7 +23,7 @@ class LiteEthMAC(Module, AutoCSR): self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2) self.comb += Port.connect(self.interface, self.core) self.ev, self.bus = self.interface.sram.ev, self.interface.bus - self.csrs = self.interface.get_csrs() + self.csrs = self.interface.get_csrs() + self.core.get_csrs() elif interface == "dma": raise NotImplementedError else: