diff --git a/lib/sata/bist.py b/lib/sata/bist.py index 2090181b7..34f0951f9 100644 --- a/lib/sata/bist.py +++ b/lib/sata/bist.py @@ -13,26 +13,22 @@ class SATABIST(Module): self.ctrl_errors = Signal(32) self.data_errors = Signal(32) - counter = Counter(bits_sign=32) - ctrl_error_counter = Counter(self.ctrl_errors, bits_sign=32) - data_error_counter = Counter(self.data_errors, bits_sign=32) - self.submodules += counter, data_error_counter, ctrl_error_counter + self.counter = counter = Counter(bits_sign=32) + self.ctrl_error_counter = Counter(self.ctrl_errors, bits_sign=32) + self.data_error_counter = Counter(self.data_errors, bits_sign=32) - scrambler = InsertReset(Scrambler()) - self.submodules += scrambler + self.scrambler = scrambler = InsertReset(Scrambler()) self.comb += [ scrambler.reset.eq(counter.reset), scrambler.ce.eq(counter.ce) ] - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - + self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", self.done.eq(1), counter.reset.eq(1), - ctrl_error_counter.reset.eq(1), - data_error_counter.reset.eq(1), + self.ctrl_error_counter.reset.eq(1), + self.data_error_counter.reset.eq(1), If(self.start, NextState("SEND_WRITE_CMD_AND_DATA") ) @@ -54,7 +50,7 @@ class SATABIST(Module): sink.ack.eq(1), If(sink.stb, If(~sink.write | ~sink.success | sink.failed, - ctrl_error_counter.ce.eq(1) + self.ctrl_error_counter.ce.eq(1) ), NextState("SEND_READ_CMD") ) @@ -74,7 +70,7 @@ class SATABIST(Module): counter.reset.eq(1), If(sink.stb & sink.read, If(~sink.read | ~sink.success | sink.failed, - ctrl_error_counter.ce.eq(1) + self.ctrl_error_counter.ce.eq(1) ), NextState("RECEIVE_READ_DATA") ) @@ -84,7 +80,7 @@ class SATABIST(Module): If(sink.stb, counter.ce.eq(1), If(sink.data != scrambler.value, - data_error_counter.ce.eq(1) + self.data_error_counter.ce.eq(1) ), If(sink.eop, NextState("IDLE") diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py index cc9fc1d20..5d7b63483 100644 --- a/lib/sata/command/__init__.py +++ b/lib/sata/command/__init__.py @@ -31,9 +31,7 @@ class SATACommandTX(Module): transport.sink.control.eq(0), ] - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - + self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", If(sink.stb & sink.sop, If(sink.write, @@ -127,9 +125,7 @@ class SATACommandRX(Module): dma_activate = Signal() - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - + self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", transport.source.ack.eq(1), If(from_tx.write, @@ -211,9 +207,7 @@ class SATACommandRX(Module): ) ) - out_fsm = FSM(reset_state="IDLE") - self.submodules += out_fsm - + self.out_fsm = out_fsm = FSM(reset_state="IDLE") out_fsm.act("IDLE", If(cmd_fifo.source.stb & cmd_fifo.source.write, NextState("PRESENT_WRITE_RESPONSE"), diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py index 535eda49b..753fd00ff 100644 --- a/lib/sata/link/__init__.py +++ b/lib/sata/link/__init__.py @@ -16,8 +16,7 @@ class SATALinkTX(Module): ### - fsm = FSM(reset_state="IDLE") - self.submodules += fsm + self.fsm = fsm = FSM(reset_state="IDLE") # insert CRC crc = SATACRCInserter(link_description(32)) @@ -35,8 +34,7 @@ class SATALinkTX(Module): # inserter CONT and scrambled data between # CONT and next primitive - cont = SATACONTInserter(phy_description(32), disable=True) - self.submodules += cont + self.cont = cont = SATACONTInserter(phy_description(32), disable=True) # datas / primitives mux insert = Signal(32) @@ -114,12 +112,10 @@ class SATALinkRX(Module): ### - fsm = FSM(reset_state="IDLE") - self.submodules += fsm + self.fsm = fsm = FSM(reset_state="IDLE") # CONT remover - cont = SATACONTRemover(phy_description(32)) - self.submodules += cont + self.cont = cont = SATACONTRemover(phy_description(32)) self.comb += Record.connect(phy.source, cont.sink) # datas / primitives detection @@ -131,12 +127,10 @@ class SATALinkRX(Module): ) # descrambler - scrambler = SATAScrambler(link_description(32)) - self.submodules += scrambler + self.scrambler = scrambler = SATAScrambler(link_description(32)) # check CRC - crc = SATACRCChecker(link_description(32)) - self.submodules += crc + self.crc = crc = SATACRCChecker(link_description(32)) sop = Signal() self.sync += \ diff --git a/lib/sata/link/cont.py b/lib/sata/link/cont.py index 9ab28e250..e1c04af75 100644 --- a/lib/sata/link/cont.py +++ b/lib/sata/link/cont.py @@ -13,8 +13,7 @@ class SATACONTInserter(Module): if disable: self.comb += Record.connect(self.sink, self.source) else: - counter = Counter(max=4) - self.submodules += counter + self.counter = counter = Counter(max=4) is_data = Signal() was_data = Signal() @@ -43,8 +42,7 @@ class SATACONTInserter(Module): ) # scrambler - scrambler = InsertReset(Scrambler()) - self.submodules += scrambler + self.scrambler = scrambler = InsertReset(Scrambler()) # Datapath self.comb += [ diff --git a/lib/sata/phy/ctrl.py b/lib/sata/phy/ctrl.py index 44e88544c..e77c11277 100644 --- a/lib/sata/phy/ctrl.py +++ b/lib/sata/phy/ctrl.py @@ -40,9 +40,7 @@ class SATAPHYHostCtrl(Module): align_detect = Signal() non_align_cnt = Signal(4) - fsm = FSM(reset_state="RESET") - self.submodules += fsm - + self.fsm = fsm = FSM(reset_state="RESET") fsm.act("RESET", trx.tx_idle.eq(1), retry_timeout.load.eq(1), @@ -177,9 +175,7 @@ class SATAPHYDeviceCtrl(Module): align_timeout = SATAPHYHostCtrlTimeout(us(873, clk_freq)) self.submodules += align_timeout, retry_timeout - fsm = FSM(reset_state="RESET") - self.submodules += fsm - + self.fsm = fsm = FSM(reset_state="RESET") fsm.act("RESET", trx.tx_idle.eq(1), retry_timeout.load.eq(1), diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py index abb07cc49..a4fd4bd7a 100644 --- a/lib/sata/transport/__init__.py +++ b/lib/sata/transport/__init__.py @@ -27,8 +27,7 @@ class SATATransportTX(Module): cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len) encoded_cmd = Signal(cmd_ndwords*32) - counter = Counter(max=cmd_ndwords+1) - self.submodules += counter + self.counter = counter = Counter(max=cmd_ndwords+1) cmd_len = Signal(counter.width) cmd_with_data = Signal() @@ -40,9 +39,7 @@ class SATATransportTX(Module): def test_type(name): return sink.type == fis_types[name] - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - + self.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", counter.reset.eq(1), If(sink.stb & sink.sop, @@ -120,8 +117,7 @@ class SATATransportRX(Module): cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len, fis_data_cmd_len) encoded_cmd = Signal(cmd_ndwords*32) - counter = Counter(max=cmd_ndwords+1) - self.submodules += counter + self.counter = counter = Counter(max=cmd_ndwords+1) cmd_len = Signal(counter.width) @@ -133,8 +129,7 @@ class SATATransportRX(Module): def test_type(name): return link.source.d[:8] == fis_types[name] - fsm = FSM(reset_state="IDLE") - self.submodules += fsm + self.fsm = fsm = FSM(reset_state="IDLE") data_sop = Signal()