From 61e605da92d04b9923dc68f1f2d45bb9c171ab12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Fri, 29 Jan 2021 11:31:40 +0100 Subject: [PATCH] litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl --- litex/tools/litex_sim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index ccb30e9bb..81a3f7dc6 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -114,7 +114,7 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq): elif memtype in ["DDR2", "DDR3"]: # Settings from s7ddrphy tck = 2/(2*nphases*clk_freq) - cl, cwl = get_cl_cw(memtype, tck) + cl, cwl = get_default_cl_cwl(memtype, tck) cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl) @@ -124,7 +124,7 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq): elif memtype == "DDR4": # Settings from usddrphy tck = 2/(2*nphases*clk_freq) - cl, cwl = get_cl_cw(memtype, tck) + cl, cwl = get_default_cl_cwl(memtype, tck) cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)