From 6a4e3bb5c06ff82be33116c25a48f68f69eed19d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Dec 2015 11:40:27 +0100 Subject: [PATCH] build/xilinx/vivado: use build_name as top in synth_design --- litex/build/xilinx/vivado.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index 032b78bbe..f199c075d 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -87,7 +87,7 @@ class XilinxVivadoToolchain: tcl.append("read_xdc {}.xdc".format(build_name)) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) - tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths))) + tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths))) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name)) tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name)) tcl.append("place_design")