diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index b748ebbf1..524d7984d 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -97,7 +97,11 @@ class XilinxVivadoToolchain:
 
         tcl.append("read_xdc {}.xdc".format(build_name))
         tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
-        tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
+        if platform.verilog_include_paths:
+            synth_design_extra = "-include_dirs {{{}}}".format(" ".join(platform.verilog_include_paths))
+        else:
+            synth_design_extra = ""
+        tcl.append("synth_design -top {} -part {} {}".format(build_name, platform.device, synth_design_extra))
         tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
         tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
         tcl.append("place_design")