From 6ac410a4627e983a45d648c95e1cec89f953470a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 18 Feb 2021 17:55:53 +0100 Subject: [PATCH] cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term. --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 6e10710a4..a029e458a 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -444,7 +444,7 @@ class UARTCrossover(UART): def __init__(self, **kwargs): assert kwargs.get("phy", None) == None UART.__init__(self, **kwargs) - self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True) + self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=16, rx_fifo_rx_we=True) self.comb += [ self.source.connect(self.xover.sink), self.xover.source.connect(self.sink)