diff --git a/litex/soc/cores/dma.py b/litex/soc/cores/dma.py
index 969109f6d..99b9b7dcc 100644
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@@ -182,7 +182,6 @@ class WishboneDMAWriter(Module, AutoCSR):
         self.submodules += fsm
         self.comb += fsm.reset.eq(~self._enable.storage)
         fsm.act("IDLE",
-            self.sink.ready.eq(1),
             NextValue(offset, 0),
             NextState("RUN"),
         )