From 6b0e525b8ced3c072e942d1a940c6c6cd4be9880 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Feb 2015 09:25:36 +0100 Subject: [PATCH] make packetizer/depacketizer more generic (remove width limitation) --- liteeth/common.py | 5 +++-- liteeth/generic/depacketizer.py | 8 +++++--- liteeth/generic/packetizer.py | 14 ++++++++------ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/liteeth/common.py b/liteeth/common.py index 9c4bc52c5..e3ba7547f 100644 --- a/liteeth/common.py +++ b/liteeth/common.py @@ -88,7 +88,7 @@ udp_protocol = 0x11 etherbone_magic = 0x4e6f etherbone_version = 1 etherbone_header_len = 8 -etherbone_header = [ +etherbone_header = { "magic": HField( 0, 0, 16), "portsize": HField( 2, 0, 4), "addrsize": HField( 2, 4, 4), @@ -105,7 +105,8 @@ etherbone_header = [ "rcount": HField( 6, 0, 8), "wcount": HField( 7, 0, 8) -] +} + def reverse_bytes(v): n = math.ceil(flen(v)/8) diff --git a/liteeth/generic/depacketizer.py b/liteeth/generic/depacketizer.py index 64a1974ef..d5fd97139 100644 --- a/liteeth/generic/depacketizer.py +++ b/liteeth/generic/depacketizer.py @@ -14,13 +14,15 @@ class LiteEthDepacketizer(Module): self.source = source = Source(source_description) self.header = Signal(header_length*8) ### + dw = flen(sink.data) + shift = Signal() - counter = Counter(max=header_length) + counter = Counter(max=header_length//(dw//8)) self.submodules += counter self.sync += \ If(shift, - self.header.eq(Cat(self.header[8:], sink.data)) + self.header.eq(Cat(self.header[dw:], sink.data)) ) fsm = FSM(reset_state="IDLE") @@ -39,7 +41,7 @@ class LiteEthDepacketizer(Module): If(sink.stb, counter.ce.eq(1), shift.eq(1), - If(counter.value == header_length-2, + If(counter.value == header_length//(dw//8)-2, NextState("COPY") ) ) diff --git a/liteeth/generic/packetizer.py b/liteeth/generic/packetizer.py index ac9cc6207..7ac0beb4f 100644 --- a/liteeth/generic/packetizer.py +++ b/liteeth/generic/packetizer.py @@ -14,10 +14,12 @@ class LiteEthPacketizer(Module): self.source = source = Source(source_description) self.header = Signal(header_length*8) ### + dw = flen(self.sink.data) + header_reg = Signal(header_length*8) load = Signal() shift = Signal() - counter = Counter(max=header_length) + counter = Counter(max=header_length//(dw//8)) self.submodules += counter self.comb += _encode_header(header_type, self.header, sink) @@ -25,7 +27,7 @@ class LiteEthPacketizer(Module): If(load, header_reg.eq(self.header) ).Elif(shift, - header_reg.eq(Cat(header_reg[8:], Signal(8))) + header_reg.eq(Cat(header_reg[dw:], Signal(dw))) ) ] @@ -40,7 +42,7 @@ class LiteEthPacketizer(Module): source.stb.eq(1), source.sop.eq(1), source.eop.eq(0), - source.data.eq(self.header[:8]), + source.data.eq(self.header[:dw]), If(source.stb & source.ack, load.eq(1), NextState("SEND_HEADER"), @@ -50,12 +52,12 @@ class LiteEthPacketizer(Module): fsm.act("SEND_HEADER", source.stb.eq(1), source.sop.eq(0), - source.eop.eq(sink.eop & (counter.value == header_length-2)), - source.data.eq(header_reg[8:16]), + source.eop.eq(sink.eop & (counter.value == header_length//(dw//8)-2)), + source.data.eq(header_reg[dw:2*dw]), If(source.stb & source.ack, shift.eq(1), counter.ce.eq(1), - If(counter.value == header_length-2, + If(counter.value == header_length//(dw//8)-2, NextState("COPY") ) )