From 6b127828166b0fbeba7f1af7545fef772ce8bbb7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Dec 2014 00:08:22 +0100 Subject: [PATCH] read/write seems OK with CommandGenerator --- targets/test.py | 51 ++++++++++++++++++++++++------------------- test/test_identify.py | 19 +++++++++------- test/test_read.py | 20 ++++++++++------- test/test_write.py | 20 ++++++++++------- 4 files changed, 64 insertions(+), 46 deletions(-) diff --git a/targets/test.py b/targets/test.py index e32de9033..8c7798ff7 100644 --- a/targets/test.py +++ b/targets/test.py @@ -215,6 +215,13 @@ class CommandGenerator(Module, AutoCSR): NextState("WAIT_WRITE_ACK") ) ) + self.sync += [ + If(fsm.ongoing("IDLE"), + cnt.eq(0) + ).Elif(sata_con.sink.stb & sata_con.sink.stb, + cnt.eq(cnt+1) + ) + ] fsm.act("WAIT_WRITE_ACK", # XXX: add check of success / failed If(sata_con.source.stb & sata_con.source.eop, @@ -312,16 +319,16 @@ class TestDesign(UART2WB, AutoCSR): self.sata_con.sink.read, self.sata_con.sink.identify, - #self.sata_con.source.stb, - #self.sata_con.source.sop, - #self.sata_con.source.eop, - #self.sata_con.source.ack, - #self.sata_con.source.write, - #self.sata_con.source.read, - #self.sata_con.source.identify, - #self.sata_con.source.success, - #self.sata_con.source.failed, - #self.sata_con.source.data, + self.sata_con.source.stb, + self.sata_con.source.sop, + self.sata_con.source.eop, + self.sata_con.source.ack, + self.sata_con.source.write, + self.sata_con.source.read, + self.sata_con.source.identify, + self.sata_con.source.success, + self.sata_con.source.failed, + self.sata_con.source.data, #self.sata_con.link.source.stb, #self.sata_con.link.source.sop, @@ -337,19 +344,19 @@ class TestDesign(UART2WB, AutoCSR): #self.sata_con.link.rx.scrambler.sink.d, #self.sata_con.link.rx.scrambler.sink.error, - self.sata_con.link.rx.scrambler.sink.stb, - self.sata_con.link.rx.scrambler.sink.sop, - self.sata_con.link.rx.scrambler.sink.eop, - self.sata_con.link.rx.scrambler.sink.ack, - self.sata_con.link.rx.scrambler.sink.d, - self.sata_con.link.rx.scrambler.sink.error, + #self.sata_con.link.rx.crc.sink.stb, + #self.sata_con.link.rx.crc.sink.sop, + #self.sata_con.link.rx.crc.sink.eop, + #self.sata_con.link.rx.crc.sink.ack, + #self.sata_con.link.rx.crc.sink.d, + #self.sata_con.link.rx.crc.sink.error, - self.sata_con.link.rx.scrambler.source.stb, - self.sata_con.link.rx.scrambler.source.sop, - self.sata_con.link.rx.scrambler.source.eop, - self.sata_con.link.rx.scrambler.source.ack, - self.sata_con.link.rx.scrambler.source.d, - self.sata_con.link.rx.scrambler.source.error, + self.sata_con.link.rx.crc.source.stb, + self.sata_con.link.rx.crc.source.sop, + self.sata_con.link.rx.crc.source.eop, + self.sata_con.link.rx.crc.source.ack, + self.sata_con.link.rx.crc.source.d, + self.sata_con.link.rx.crc.source.error, self.command_tx_fsm_state, self.transport_tx_fsm_state, diff --git a/test/test_identify.py b/test/test_identify.py index 24f1a4de4..3fcba0b36 100644 --- a/test/test_identify.py +++ b/test/test_identify.py @@ -8,16 +8,19 @@ wb.open() regs = wb.regs ### -#trigger0 = mila.sata_con_sink_payload_identify_o*1 -#mask0 = mila.sata_con_sink_payload_identify_m +cond = { + #"sata_phy_source_source_payload_data" : primitives["R_RDY"], + #"sata_phy_source_source_payload_data" : primitives["R_OK"], + "sata_phy_source_source_payload_data" : primitives["X_RDY"], +} -#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"] -#mask0 = mila.sata_phy_source_source_payload_data_m +trigger = 0 +mask = 0 +for k, v in cond.items(): + trigger |= getattr(mila, k+"_o")*v + mask |= getattr(mila, k+"_m") -trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"] -mask0 = mila.sata_phy_source_source_payload_data_m - -mila.prog_term(port=0, trigger=trigger0, mask=mask0) +mila.prog_term(port=0, trigger=trigger, mask=mask) mila.prog_sum("term") # Trigger / wait / receive diff --git a/test/test_read.py b/test/test_read.py index 155c5487d..632469ee6 100644 --- a/test/test_read.py +++ b/test/test_read.py @@ -8,16 +8,20 @@ wb.open() regs = wb.regs ### -#trigger0 = mila.sata_con_sink_payload_read_o*1 -#mask0 = mila.sata_con_sink_payload_read_m +cond = { + #"sata_phy_source_source_payload_data" : primitives["R_RDY"], + #"sata_phy_source_source_payload_data" : primitives["R_OK"], + #"sata_phy_source_source_payload_data" : primitives["X_RDY"], + "sata_con_source_source_stb" : 1, +} -#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"] -#mask0 = mila.sata_phy_source_source_payload_data_m +trigger = 0 +mask = 0 +for k, v in cond.items(): + trigger |= getattr(mila, k+"_o")*v + mask |= getattr(mila, k+"_m") -trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"] -mask0 = mila.sata_phy_source_source_payload_data_m - -mila.prog_term(port=0, trigger=trigger0, mask=mask0) +mila.prog_term(port=0, trigger=trigger, mask=mask) mila.prog_sum("term") # Trigger / wait / receive diff --git a/test/test_write.py b/test/test_write.py index 8c760d518..ccc3e354b 100644 --- a/test/test_write.py +++ b/test/test_write.py @@ -8,16 +8,20 @@ wb.open() regs = wb.regs ### -#trigger0 = mila.sata_con_sink_payload_write_o*1 -#mask0 = mila.sata_con_sink_payload_write_m +cond = { + #"sata_phy_source_source_payload_data" : primitives["R_RDY"], + #"sata_phy_source_source_payload_data" : primitives["R_OK"], + #"sata_phy_source_source_payload_data" : primitives["X_RDY"], + "sata_con_source_source_stb" : 1, +} -#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_RDY"] -#mask0 = mila.sata_phy_source_source_payload_data_m +trigger = 0 +mask = 0 +for k, v in cond.items(): + trigger |= getattr(mila, k+"_o")*v + mask |= getattr(mila, k+"_m") -trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"] -mask0 = mila.sata_phy_source_source_payload_data_m - -mila.prog_term(port=0, trigger=trigger0, mask=mask0) +mila.prog_term(port=0, trigger=trigger, mask=mask) mila.prog_sum("term") # Trigger / wait / receive