From 6b7026f521093ecf36416e7b3a8b60a5e545fe7c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 24 Feb 2015 01:42:56 +0100 Subject: [PATCH] add sim phy --- liteeth/phy/sim.py | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 liteeth/phy/sim.py diff --git a/liteeth/phy/sim.py b/liteeth/phy/sim.py new file mode 100644 index 000000000..3d9174cbd --- /dev/null +++ b/liteeth/phy/sim.py @@ -0,0 +1,36 @@ +from liteeth.common import * +from liteeth.generic import * + +class LiteEthPHYSimCRG(Module, AutoCSR): + def __init__(self): + self._reset = CSRStorage() + + ### + + self.clock_domains.cd_eth_rx = ClockDomain() + self.clock_domains.cd_eth_tx = ClockDomain() + self.comb += [ + self.cd_eth_rx.clk.eq(ClockSignal()), + self.cd_eth_tx.clk.eq(ClockSignal()) + ] + + reset = self._reset.storage + self.comb += [ + self.cd_eth_rx.rst.eq(reset), + self.cd_eth_tx.rst.eq(reset) + ] + +class LiteEthPHYSim(Module, AutoCSR): + def __init__(self, pads): + self.dw = 8 + self.submodules.crg = LiteEthPHYSimCRG() + self.sink = sink = Sink(eth_phy_description(8)) + self.source = source = Source(eth_phy_description(8)) + self.comb += [ + pads.source_stb.eq(self.sink.stb), + pads.source_data.eq(self.sink.data), + self.sink.ack.eq(1), + + self.source.stb.eq(pads.sink_stb), + self.source.data.eq(pads.sink_data) + ]