diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 0aef8bc96..9b363d6c8 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -336,6 +336,12 @@ class VexRiscv(CPU, AutoCSR):
             soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(
                 origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False))
 
+        base_variant = str(self.variant.split('+')[0])
+        if base_variant == "lite" or base_variant == "minimal":
+            soc.add_config("CPU_NO_DCACHE")
+        if base_variant == "minimal":
+            soc.add_config("CPU_NO_ICACHE")
+
     def use_external_variant(self, variant_filename):
         self.external_variant = True
         self.platform.add_source(variant_filename)
diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
index 1fcfb4fba..c48a9ba27 100644
--- a/litex/soc/cores/cpu/vexriscv/system.h
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -11,7 +11,7 @@ extern "C" {
 
 __attribute__((unused)) static void flush_cpu_icache(void)
 {
-#if defined(CONFIG_CPU_VARIANT_MINIMAL)
+#if defined(CONFIG_CPU_NO_ICACHE)
   /* No instruction cache */
 #else
   asm volatile(
@@ -27,7 +27,7 @@ __attribute__((unused)) static void flush_cpu_icache(void)
 
 __attribute__((unused)) static void flush_cpu_dcache(void)
 {
-#if defined(CONFIG_CPU_VARIANT_MINIMAL) || defined(CONFIG_CPU_VARIANT_LITE)
+#if defined(CONFIG_CPU_NO_DCACHE)
   /* No data cache */
 #else
   asm volatile(".word(0x500F)\n");