From 6b7ca0cff7cae7452656b3e06f0d63b347ab8699 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 7 Aug 2019 08:17:44 +0200 Subject: [PATCH] cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq --- litex/soc/cores/clock.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index a15c2ec19..ed07b8716 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -64,7 +64,7 @@ class XilinxClocking(Module, AutoCSR): config = {} for divclk_divide in range(*self.divclk_divide_range): config["divclk_divide"] = divclk_divide - for clkfbout_mult in range(*self.clkfbout_mult_frange): + for clkfbout_mult in reversed(range(*self.clkfbout_mult_frange)): all_valid = True vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide (vco_freq_min, vco_freq_max) = self.vco_freq_range