From 6bf40c40100d4eb06dfca31ac98ac39dc8a56109 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Feb 2015 17:42:05 +0100 Subject: [PATCH] mac: fix gap inserter/checker --- liteeth/mac/core/__init__.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py index 5db1feac7..9baa0c9fd 100644 --- a/liteeth/mac/core/__init__.py +++ b/liteeth/mac/core/__init__.py @@ -12,7 +12,8 @@ class LiteEthMACCore(Module, AutoCSR): # Interpacket gap tx_gap_inserter = gap.LiteEthMACGap(phy.dw) rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True) - self.submodules += tx_gap_inserter, rx_gap_checker + self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx") + self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx") tx_pipeline += [tx_gap_inserter] rx_pipeline += [rx_gap_checker] @@ -57,8 +58,8 @@ class LiteEthMACCore(Module, AutoCSR): rx_pipeline += [rx_converter] # Cross Domain Crossing - tx_cdc = AsyncFIFO(eth_phy_description(dw), 8) - rx_cdc = AsyncFIFO(eth_phy_description(dw), 8) + tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) + rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})