From 6cf1a814eb22ebebc85c82740e71b750528ba71f Mon Sep 17 00:00:00 2001 From: Antony Pavlov Date: Mon, 27 May 2019 11:17:51 +0300 Subject: [PATCH] boards: add Terasic DE2-115 initial support See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1 for board details. Signed-off-by: Antony Pavlov --- litex/boards/platforms/de2_115.py | 40 ++++++++++++ litex/boards/targets/de2_115.py | 103 ++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 litex/boards/platforms/de2_115.py create mode 100755 litex/boards/targets/de2_115.py diff --git a/litex/boards/platforms/de2_115.py b/litex/boards/platforms/de2_115.py new file mode 100644 index 000000000..b04467dd7 --- /dev/null +++ b/litex/boards/platforms/de2_115.py @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (c) 2019 Antony Pavlov + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform + +# IOs ------------------------------------------------------------------ + +_io = [ + ("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")), + + ("serial", 0, + Subsignal("tx", Pins("AB22"), IOStandard("3.3-V LVTTL")), # JP5 GPIO[0] + Subsignal("rx", Pins("AC15"), IOStandard("3.3-V LVTTL")) # JP5 GPIO[1] + ), + + ("sdram_clock", 0, Pins("AE5"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins("R6 V8 U8 P1 V5 W8 W7 AA7 Y5 Y6 R5 AA5 Y7")), + Subsignal("ba", Pins("U7 R4")), + Subsignal("cs_n", Pins("T4")), + Subsignal("cke", Pins("AA6")), + Subsignal("ras_n", Pins("U6")), + Subsignal("cas_n", Pins("V7")), + Subsignal("we_n", Pins("V6")), + Subsignal("dq", Pins("W3 W2 V4 W1 V3 V2 V1 U3 Y3 Y4 AB1 AA3 AB2 AC1 AB3 AC2")), + Subsignal("dm", Pins("U2 W4")), + IOStandard("3.3-V LVTTL") + ), +] + +# Platform ------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 20 + + def __init__(self): + AlteraPlatform.__init__(self, "EP4CE115F29C7", _io) diff --git a/litex/boards/targets/de2_115.py b/litex/boards/targets/de2_115.py new file mode 100755 index 000000000..2775a79fc --- /dev/null +++ b/litex/boards/targets/de2_115.py @@ -0,0 +1,103 @@ +#!/usr/bin/env python3 +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (C) 2019 Antony Pavlov +# +# based on litex/boards/platforms/de0nano.py +# + +import argparse + +from migen import * + +from litex.boards.platforms import de2_115 + +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * + +from litedram.modules import IS42S16320 +from litedram.phy import GENSDRPHY + +# CRG ------------------------------------------------------------------ + +class _CRG(Module): + def __init__(self, platform): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + + # # # + + self.cd_sys.clk.attr.add("keep") + self.cd_sys_ps.clk.attr.add("keep") + self.cd_por.clk.attr.add("keep") + + # power on rst + rst_n = Signal() + self.sync.por += rst_n.eq(1) + self.comb += [ + self.cd_por.clk.eq(self.cd_sys.clk), + self.cd_sys.rst.eq(~rst_n), + self.cd_sys_ps.rst.eq(~rst_n) + ] + + # sys clk / sdram clk + clk50 = platform.request("clk50") + self.comb += self.cd_sys.clk.eq(clk50) + self.specials += \ + Instance("ALTPLL", + p_BANDWIDTH_TYPE="AUTO", + p_CLK0_DIVIDE_BY=1, + p_CLK0_DUTY_CYCLE=50, + p_CLK0_MULTIPLY_BY=1, + p_CLK0_PHASE_SHIFT="-3000", + p_COMPENSATE_CLOCK="CLK0", + p_INCLK0_INPUT_FREQUENCY=20000, + p_OPERATION_MODE="ZERO_DELAY_BUFFER", + i_INCLK=clk50, + o_CLK=self.cd_sys_ps.clk, + i_ARESET=~rst_n, + i_CLKENA=0x3f, + i_EXTCLKENA=0xf, + i_FBIN=1, + i_PFDENA=1, + i_PLLENA=1, + ) + self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + +# BaseSoC -------------------------------------------------------------- + +class BaseSoC(SoCSDRAM): + def __init__(self, sys_clk_freq=int(50e6), **kwargs): + assert sys_clk_freq == int(50e6) + platform = de2_115.Platform() + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, + integrated_rom_size=0x8000, + **kwargs) + + self.submodules.crg = _CRG(platform) + + if not self.integrated_main_ram_size: + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + # ISSI IS42S16320D-7TL + sdram_module = IS42S16320(self.clk_freq, "1:1") + self.register_sdram(self.sdrphy, + sdram_module.geom_settings, + sdram_module.timing_settings) + +# Build ---------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build() + + +if __name__ == "__main__": + main()