diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 92d49a6fc..d99661d66 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -6,6 +6,7 @@ import os
 
 from migen import *
 
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -80,11 +81,9 @@ class SERV(CPU):
 
     @staticmethod
     def add_sources(platform):
-        # FIXME: add SERV as submodule
-        os.system("git clone https://github.com/olofk/serv")
-        vdir = os.path.join("serv", "rtl")
-        platform.add_source_dir(vdir)
-        platform.add_verilog_include_path(vdir)
+        vdir = get_data_mod("cpu", "serv").data_location
+        platform.add_source_dir(os.path.join(vdir, "rtl"))
+        platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
diff --git a/litex_setup.py b/litex_setup.py
index 52c2635ed..f2502abc0 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -42,6 +42,7 @@ repos = [
     ("pythondata-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-serv",        ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
 ]