From 6d11d1991bbfea63879fe6e5249ca9c7945f1277 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 13 Jun 2022 22:51:54 +0800 Subject: [PATCH] build/altera: Add derive_pll_clocks to SDC file Quartus software wants a derive_pll_clock sentence in SDC file to enable automatic PLL clock derivation, and by test this sentence is harmless even when no PLL exists. Add this sentence to to the generated SDC file. Signed-off-by: Icenowy Zheng --- litex/build/altera/quartus.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py index 762d0ed25..c4bf96ac7 100644 --- a/litex/build/altera/quartus.py +++ b/litex/build/altera/quartus.py @@ -88,6 +88,9 @@ def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_co tpl = "create_clock -name {clk} -period {period} [get_nets {{{clk}}}]" sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period))) + # Enable automatical constraint generation for PLLs + sdc.append("derive_pll_clocks") + # False path constraints for from_, to in sorted(false_paths, key=lambda x: (x[0].duid, x[1].duid)): tpl = "set_false_path -from [get_clocks {{{from_}}}] -to [get_clocks {{{to}}}]"