From 6d46a5ba05416b809e8b92595eecf13b1f68e126 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 27 Aug 2024 09:02:58 +0200 Subject: [PATCH] efinix: Fix PLL with external clock input ifacewriter --- litex/build/efinix/ifacewriter.py | 2 ++ litex/soc/cores/clock/efinix.py | 1 + 2 files changed, 3 insertions(+) diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py index e5fbe9318..4e4c84972 100644 --- a/litex/build/efinix/ifacewriter.py +++ b/litex/build/efinix/ifacewriter.py @@ -295,6 +295,8 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) else: cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \ .format(name, block["resource"], block["input_clock"], block["input_clock_name"], block["clock_no"]) + for p, val in block["input_properties"]: + cmd += 'design.set_property("{}","{}","{}")\n'.format(block["input_clock_name"], p, val) else: cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_name="{}", refclk_src="CORE")\n'.format(name, block["resource"], block["input_signal"]) cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block["input_signal"]) diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py index 63cca6839..1e8cfcadb 100644 --- a/litex/soc/cores/clock/efinix.py +++ b/litex/soc/cores/clock/efinix.py @@ -85,6 +85,7 @@ class EFINIXPLL(LiteXModule): block["input_refclk_name"] = refclk_name block["resource"] = pll_res block["clock_no"] = clock_no + block["input_properties"] = self.platform.get_pin_properties(clkin) self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no)) self.platform.get_pll_resource(pll_res) else: