From 6d6c2b4c4562ebc68dc0ded11759be39116a454c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 12 Dec 2018 09:38:10 +0100 Subject: [PATCH] soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) --- litex/soc/cores/cpu/lm32/core.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index d32d7ba64..b79a7fd6c 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -88,6 +88,7 @@ class LM32(Module): "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") + platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl")) if variant == "minimal": platform.add_verilog_include_path(os.path.join(vdir, "config_minimal")) elif variant == "lite":