diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 100ce4be7..4fcb792b8 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -88,7 +88,7 @@ class VexRiscv(CPU, AutoCSR):
         return {
             "rom":          0x00000000,
             "sram":         0x10000000,
-            "main_ram":     0xc0000000,
+            "main_ram":     0x40000000,
             "csr":          0xf0000000,
         }