diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 49951d986..06678bcb8 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -211,5 +211,6 @@ def builder_argdict(args):
         "compile_software": not args.no_compile_software,
         "compile_gateware": not args.no_compile_gateware,
         "gateware_toolchain_path": args.gateware_toolchain_path,
-        "csr_csv": args.csr_csv
+        "csr_csv": args.csr_csv,
+        "csr_json": args.csr_json,
     }
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 597b2aa2b..496435c9e 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -609,9 +609,9 @@ def soc_core_args(parser):
                         help="CPU reset address (default=0x00000000 or ROM)")
     # ROM parameters
     parser.add_argument("--integrated-rom-size", default=0x8000, type=int,
-                        help="size/enable the integrated (BIOS) ROM")
+                        help="size/enable the integrated (BIOS) ROM (default=32KB)")
     parser.add_argument("--integrated-rom-file", default=None, type=str,
-                        help="integrated (BIOS) ROM binary file (default=32KB)")
+                        help="integrated (BIOS) ROM binary file")
     # SRAM parameters
     parser.add_argument("--integrated-sram-size", default=0x1000, type=int,
                         help="size/enable the integrated SRAM (default=4KB)")