From eb49ec217e4ba1136eaef5b18b759f6a38f456a5 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 31 Jan 2020 18:53:50 +0300 Subject: [PATCH 1/2] Pass --csr-json to the Builder --- litex/soc/integration/builder.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py index 49951d986..06678bcb8 100644 --- a/litex/soc/integration/builder.py +++ b/litex/soc/integration/builder.py @@ -211,5 +211,6 @@ def builder_argdict(args): "compile_software": not args.no_compile_software, "compile_gateware": not args.no_compile_gateware, "gateware_toolchain_path": args.gateware_toolchain_path, - "csr_csv": args.csr_csv + "csr_csv": args.csr_csv, + "csr_json": args.csr_json, } From de88ed282a72021965b5aa3e6272a20f82293f56 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Fri, 31 Jan 2020 18:54:25 +0300 Subject: [PATCH 2/2] Fix argument descriptions --- litex/soc/integration/soc_core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 597b2aa2b..496435c9e 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -609,9 +609,9 @@ def soc_core_args(parser): help="CPU reset address (default=0x00000000 or ROM)") # ROM parameters parser.add_argument("--integrated-rom-size", default=0x8000, type=int, - help="size/enable the integrated (BIOS) ROM") + help="size/enable the integrated (BIOS) ROM (default=32KB)") parser.add_argument("--integrated-rom-file", default=None, type=str, - help="integrated (BIOS) ROM binary file (default=32KB)") + help="integrated (BIOS) ROM binary file") # SRAM parameters parser.add_argument("--integrated-sram-size", default=0x1000, type=int, help="size/enable the integrated SRAM (default=4KB)")