diff --git a/litex/build/altera/platform.py b/litex/build/altera/platform.py
index 6838e5531..ef85f47a6 100644
--- a/litex/build/altera/platform.py
+++ b/litex/build/altera/platform.py
@@ -2,6 +2,7 @@
 # This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
 # License: BSD
 
+import os
 
 from litex.build.generic_platform import GenericPlatform
 from litex.build.altera import common, quartus
@@ -13,11 +14,15 @@ class AlteraPlatform(GenericPlatform):
 
     def __init__(self, *args, toolchain="quartus", **kwargs):
         GenericPlatform.__init__(self, *args, **kwargs)
+        self.ips = set()
         if toolchain == "quartus":
             self.toolchain = quartus.AlteraQuartusToolchain()
         else:
             raise ValueError("Unknown toolchain")
 
+    def add_ip(self, filename):
+        self.ips.add((os.path.abspath(filename)))
+
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict(common.altera_special_overrides)
         so.update(special_overrides)
diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py
index a8a7f64af..40f0681a7 100644
--- a/litex/build/altera/quartus.py
+++ b/litex/build/altera/quartus.py
@@ -89,11 +89,13 @@ def _build_sdc(clocks, false_paths, vns, build_name):
     tools.write_to_file("{}.sdc".format(build_name), "\n".join(lines))
 
 
-def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
+def _build_files(device, ips, sources, vincpaths, named_sc, named_pc, build_name):
     lines = []
+    for filename in ips:
+           lines.append("set_global_assignment -name QSYS_FILE {path} ".format(
+                path=filename.replace("\\", "/")))
     for filename, language, library in sources:
-        # Enforce use of SystemVerilog
-        # (Quartus does not support global parameters in Verilog)
+        # Enforce use of SystemVerilog since Quartus does not support global parameters in Verilog
         if language == "verilog":
             language = "systemverilog"
         lines.append(
@@ -168,9 +170,10 @@ class AlteraQuartusToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog", "work")}
+        platform.add_source(v_file)
         _build_files(platform.device,
-                     sources,
+                     platform.ips,
+                     platform.sources,
                      platform.verilog_include_paths,
                      named_sc,
                      named_pc,