From 6e883b4513232e9cf8b017f7aaa08b3f2de7b062 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 25 Feb 2021 09:10:26 +0100 Subject: [PATCH] tools/litex_sim: Add boot to main_ram when sdram_init contents provided. --- litex/tools/litex_sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index cbb503d91..921e676e8 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -448,7 +448,7 @@ def main(): trace_reset_on = trace_start > 0 or trace_end > 0, sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness), **soc_kwargs) - if args.ram_init is not None: + if args.ram_init is not None or args.sdram_init is not None: soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) if args.with_ethernet: for i in range(4):