diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py index 4ba8773c2..7cc208b08 100644 --- a/litex/soc/cores/cpu/eos_s3/core.py +++ b/litex/soc/cores/cpu/eos_s3/core.py @@ -47,7 +47,7 @@ class EOS_S3(CPU): self.platform = platform self.reset = Signal() self.interrupt = Signal(4) - self.pbus = wishbone.Interface(data_width=32, adr_width=15, addressing="word") + self.pbus = wishbone.Interface(data_width=32, adr_width=15, addressing="byte") self.periph_buses = [self.pbus] self.memory_buses = [] @@ -84,7 +84,7 @@ class EOS_S3(CPU): # ----------- i_WB_CLK = ClockSignal("eos_s3_0"), o_WB_RST = pbus_rst, - o_WBs_ADR = Cat(Signal(2), self.pbus.adr), + o_WBs_ADR = self.pbus.adr, o_WBs_CYC = self.pbus.cyc, o_WBs_BYTE_STB = self.pbus.sel, o_WBs_WE = self.pbus.we, diff --git a/litex/soc/cores/cpu/femtorv/core.py b/litex/soc/cores/cpu/femtorv/core.py index 3f118fa8a..4f3c6142c 100644 --- a/litex/soc/cores/cpu/femtorv/core.py +++ b/litex/soc/cores/cpu/femtorv/core.py @@ -71,7 +71,7 @@ class FemtoRV(CPU): self.variant = variant self.human_name = f"FemtoRV-{variant.upper()}" self.reset = Signal() - self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -119,7 +119,7 @@ class FemtoRV(CPU): self.fsm = fsm = FSM(reset_state="WAIT") fsm.act("WAIT", # Latch Address + Bytes to Words conversion. - NextValue(idbus.adr, mbus.addr[2:]), + NextValue(idbus.adr, mbus.addr), # Latch Wdata/WMask. NextValue(idbus.dat_w, mbus.wdata), diff --git a/litex/soc/cores/cpu/firev/core.py b/litex/soc/cores/cpu/firev/core.py index b18ffe0e9..5904110a2 100644 --- a/litex/soc/cores/cpu/firev/core.py +++ b/litex/soc/cores/cpu/firev/core.py @@ -59,7 +59,7 @@ class FireV(CPU): self.variant = variant self.human_name = f"FireV-{variant.upper()}" self.reset = Signal() - self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -115,7 +115,7 @@ class FireV(CPU): ) self.comb += [ idbus.we.eq(mbus.out_ram_rw), - idbus.adr.eq(mbus.out_ram_addr[2:]), + idbus.adr.eq(mbus.out_ram_addr), idbus.sel.eq(mbus.out_ram_wmask), idbus.dat_w.eq(mbus.out_ram_data_in), diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index e8b46d797..b3e88077e 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -57,7 +57,7 @@ class OBI2Wishbone(Module): # On OBI request: If(obi.req, # Drive Wishbone bus from OBI bus. - wb.adr.eq(obi.addr[2:32]), + wb.adr.eq( obi.addr), wb.stb.eq( 1), wb.dat_w.eq( obi.wdata), wb.cyc.eq( 1), @@ -77,7 +77,7 @@ class OBI2Wishbone(Module): ) fsm.act("ACK", # Drive Wishbone bus from stored OBI bus values. - wb.adr.eq(addr[2:32]), + wb.adr.eq( addr), wb.stb.eq( 1), wb.dat_w.eq( wdata), wb.cyc.eq( 1), @@ -121,8 +121,8 @@ class Ibex(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [self.ibus, self.dbus] self.memory_buses = [] self.interrupt = Signal(15) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 2dd157dff..a6557f71a 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -51,8 +51,8 @@ class LM32(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.interrupt = Signal(32) self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -68,7 +68,7 @@ class LM32(CPU): i_interrupt=self.interrupt, # IBus. - o_I_ADR_O = Cat(Signal(2), ibus.adr), + o_I_ADR_O = ibus.adr, o_I_DAT_O = ibus.dat_w, o_I_SEL_O = ibus.sel, o_I_CYC_O = ibus.cyc, @@ -82,7 +82,7 @@ class LM32(CPU): i_I_RTY_I = 0, # DBus. - o_D_ADR_O = Cat(Signal(2), dbus.adr), + o_D_ADR_O = dbus.adr, o_D_DAT_O = dbus.dat_w, o_D_SEL_O = dbus.sel, o_D_CYC_O = dbus.cyc, diff --git a/litex/soc/cores/cpu/marocchino/core.py b/litex/soc/cores/cpu/marocchino/core.py index 7b1b7eb07..150e111d2 100644 --- a/litex/soc/cores/cpu/marocchino/core.py +++ b/litex/soc/cores/cpu/marocchino/core.py @@ -84,8 +84,8 @@ class Marocchino(CPU): self.variant = variant self.reset = Signal() self.interrupt = Signal(32) - self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -123,7 +123,7 @@ class Marocchino(CPU): i_cpu_rst = ResetSignal("sys") | self.reset, # IBus. - o_iwbm_adr_o = Cat(Signal(2), ibus.adr), + o_iwbm_adr_o = ibus.adr, o_iwbm_stb_o = ibus.stb, o_iwbm_cyc_o = ibus.cyc, o_iwbm_sel_o = ibus.sel, @@ -137,7 +137,7 @@ class Marocchino(CPU): i_iwbm_rty_i = 0, # DBus. - o_dwbm_adr_o = Cat(Signal(2), dbus.adr), + o_dwbm_adr_o = dbus.adr, o_dwbm_stb_o = dbus.stb, o_dwbm_cyc_o = dbus.cyc, o_dwbm_sel_o = dbus.sel, diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index b198dd379..349be5ca9 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -84,8 +84,8 @@ class MOR1KX(CPU): self.variant = variant self.reset = Signal() self.interrupt = Signal(32) - self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -160,7 +160,7 @@ class MOR1KX(CPU): i_irq_i=self.interrupt, # IBus. - o_iwbm_adr_o = Cat(Signal(2), ibus.adr), + o_iwbm_adr_o = ibus.adr, o_iwbm_dat_o = ibus.dat_w, o_iwbm_sel_o = ibus.sel, o_iwbm_cyc_o = ibus.cyc, @@ -174,7 +174,7 @@ class MOR1KX(CPU): i_iwbm_rty_i = 0, # DBus. - o_dwbm_adr_o = Cat(Signal(2), dbus.adr), + o_dwbm_adr_o = dbus.adr, o_dwbm_dat_o = dbus.dat_w, o_dwbm_sel_o = dbus.sel, o_dwbm_cyc_o = dbus.cyc, diff --git a/litex/soc/cores/cpu/neorv32/core.py b/litex/soc/cores/cpu/neorv32/core.py index 1de021f2e..a3f953048 100644 --- a/litex/soc/cores/cpu/neorv32/core.py +++ b/litex/soc/cores/cpu/neorv32/core.py @@ -75,7 +75,7 @@ class NEORV32(CPU): self.variant = variant self.human_name = f"NEORV32-{variant}" self.reset = Signal() - self.ibus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.ibus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -98,7 +98,7 @@ class NEORV32(CPU): i_mext_irq_i = 0, # I/D Wishbone Bus. - o_wb_adr_o = Cat(Signal(2), idbus.adr), + o_wb_adr_o = idbus.adr, i_wb_dat_i = idbus.dat_r, o_wb_dat_o = idbus.dat_w, o_wb_we_o = idbus.we, diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 3d33a4038..d7d5f4a1b 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -74,7 +74,7 @@ class PicoRV32(CPU): self.trap = Signal() self.reset = Signal() self.interrupt = Signal(32) - self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -166,7 +166,7 @@ class PicoRV32(CPU): # Adapt Memory Interface to Wishbone. self.comb += [ - idbus.adr.eq(mem_addr[2:]), + idbus.adr.eq(mem_addr), idbus.dat_w.eq(mem_wdata), idbus.we.eq(mem_wstrb != 0), idbus.sel.eq(mem_wstrb), diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index 4de458a2b..0e7835122 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -59,8 +59,8 @@ class SERV(CPU): self.platform = platform self.variant = variant self.reset = Signal() - self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="word") + self.ibus = ibus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") + self.dbus = dbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte") self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus). self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM). @@ -68,20 +68,20 @@ class SERV(CPU): self.cpu_params = dict( # Clk / Rst - i_clk = ClockSignal(), - i_i_rst = ResetSignal() | self.reset, + i_clk = ClockSignal("sys"), + i_i_rst = ResetSignal("sys") | self.reset, # Timer IRQ. i_i_timer_irq = 0, # Ibus. - o_o_ibus_adr = Cat(Signal(2), ibus.adr), + o_o_ibus_adr = ibus.adr, o_o_ibus_cyc = ibus.cyc, i_i_ibus_rdt = ibus.dat_r, i_i_ibus_ack = ibus.ack, # Dbus. - o_o_dbus_adr = Cat(Signal(2), dbus.adr), + o_o_dbus_adr = dbus.adr, o_o_dbus_dat = dbus.dat_w, o_o_dbus_sel = dbus.sel, o_o_dbus_we = dbus.we,