From f0b0d8db2939ea9a00495ab75021a589b605dfe3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jun 2024 17:01:40 +0200 Subject: [PATCH 1/3] linux dts: add vexii clint support --- litex/tools/litex_json2dts_linux.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py index 7547cd7d0..a2af5e725 100755 --- a/litex/tools/litex_json2dts_linux.py +++ b/litex/tools/litex_json2dts_linux.py @@ -328,7 +328,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic # Interrupt Controller ------------------------------------------------------------------------- - if (cpu_arch == "riscv") and ("rocket" in cpu_name): + if (cpu_arch == "riscv") and ("rocket" in cpu_name or "vexiiriscv" in cpu_name): # FIXME : L4 definitiion? # CHECKME: interrupts-extended. dts += """ From 87ae5db16b70692bf7ef2d270ec47a19657c50d6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 10 Jun 2024 18:10:13 +0200 Subject: [PATCH 2/3] linux dts: add vexii clint support --- litex/tools/litex_json2dts_linux.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py index a2af5e725..20e4baa4f 100755 --- a/litex/tools/litex_json2dts_linux.py +++ b/litex/tools/litex_json2dts_linux.py @@ -328,7 +328,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic # Interrupt Controller ------------------------------------------------------------------------- - if (cpu_arch == "riscv") and ("rocket" in cpu_name or "vexiiriscv" in cpu_name): + if (cpu_arch == "riscv") and (cpu_name in ["rocket", "vexiiriscv"]): # FIXME : L4 definitiion? # CHECKME: interrupts-extended. dts += """ From 8c80a6c19c5ec2a8e599b4f448d4446fb24404cd Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 11 Jun 2024 13:08:25 +0200 Subject: [PATCH 3/3] linux dts: rework "rocket" in cpu_name into cpu_name == "rocket" --- litex/tools/litex_json2dts_linux.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py index 20e4baa4f..57b58c4c3 100755 --- a/litex/tools/litex_json2dts_linux.py +++ b/litex/tools/litex_json2dts_linux.py @@ -50,7 +50,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic if "d" in cpu_isa[5:]: cpu_isa_extensions += ", \"c\"" # rocket specific extensions - if "rocket" in cpu_name: + if cpu_name == "rocket": cpu_isa_extensions += ", \"zicsr\", \"zifencei\", \"zihpm\"" cpu_mmu = d["constants"].get("config_cpu_mmu", None) @@ -171,7 +171,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic i_tlb_ways = d["constants"]["config_cpu_itlb_ways"]) # Rocket specific attributes - if ("rocket" in cpu_name): + if (cpu_name == "rocket"): extra_attr = """ hardware-exec-breakpoint-count = <1>; next-level-cache = <&memory>; @@ -343,7 +343,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic clint_base=d["memories"]["clint"]["base"], cpu_mapping =("\n" + " "*20).join(["&L{} 3 &L{} 7".format(cpu, cpu) for cpu in range(ncpus)])) if cpu_arch == "riscv": - if "rocket" in cpu_name: + if cpu_name == "rocket": extra_attr = """ reg-names = "control"; riscv,max-priority = <7>; @@ -377,7 +377,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic status = "okay"; }; """ - if (cpu_arch == "riscv") and ("rocket" in cpu_name): + if (cpu_arch == "riscv") and (cpu_name == "rocket"): dts += """ dbg_ctl: debug-controller@0 {{ compatible = "sifive,debug-013", "riscv,debug-013"; @@ -404,7 +404,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic if "uart" in d["csr_bases"]: aliases["serial0"] = "liteuart0" - it_incr = {True: 1, False: 0}["rocket" in cpu_name] + it_incr = {True: 1, False: 0}[cpu_name == "rocket"] dts += """ liteuart0: serial@{uart_csr_base:x} {{ compatible = "litex,liteuart"; @@ -421,7 +421,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic idx = (0 if i == '' else i) ethphy_name = "ethphy" + str(i) ethmac_name = "ethmac" + str(i) - it_incr = {True: 1, False: 0}["rocket" in cpu_name] + it_incr = {True: 1, False: 0}[cpu_name == "rocket"] if ethphy_name in d["csr_bases"] and ethmac_name in d["csr_bases"]: dts += """ mac{idx}: mac@{ethmac_csr_base:x} {{