From 6ee39b4712f2e23ccc9a1f2609b13b991148489e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 17 Mar 2023 21:33:37 +0100 Subject: [PATCH] cores/cpu/vexriscv_smp/naxrisv: Fix/Shift IRQ numbering since 0 is reserved. --- litex/soc/cores/cpu/naxriscv/core.py | 9 +++++---- litex/soc/cores/cpu/vexriscv_smp/core.py | 10 ++++++---- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 86072df10..46958ea47 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -181,6 +181,10 @@ class NaxRiscv(CPU): i_peripheral_dbus_rresp = dbus.r.resp, ) + # IRQs (Note: 0 is reserved as a "No IRQ"). + self.interrupts.update({"uart" : 1}) + self.interrupts.update({"timer0" : 2}) + def set_reset_address(self, reset_address): self.reset_address = reset_address @@ -293,13 +297,10 @@ class NaxRiscv(CPU): platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") def add_soc_components(self, soc): - # Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI. + # Set UART/Timer0 CSRs to the ones used by OpenSBI. soc.csr.add("uart", n=2) soc.csr.add("timer0", n=3) - soc.irq.add("uart", n=0) - soc.irq.add("timer0", n=1) - # Add OpenSBI region. soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True)) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index c5f4f861b..b4fe21734 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -330,6 +330,7 @@ class VexRiscvSMP(CPU): o_peripheral_BTE = pbus.bte ) + # DMA. if VexRiscvSMP.coherent_dma: self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width) dma_bus_stall = Signal() @@ -355,6 +356,10 @@ class VexRiscvSMP(CPU): ) ] + # IRQs (Note: 0 is reserved as a "No IRQ"). + self.interrupts.update({"uart" : 1}) + self.interrupts.update({"timer0" : 2}) + def set_reset_address(self, reset_address): self.reset_address = reset_address assert reset_address == 0x0000_0000 @@ -389,13 +394,10 @@ class VexRiscvSMP(CPU): def add_soc_components(self, soc): if self.variant == "linux": - # Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI. + # Set UART/Timer0 CSRs to the ones used by OpenSBI. soc.csr.add("uart", n=2) soc.csr.add("timer0", n=3) - soc.irq.add("uart", n=0) - soc.irq.add("timer0", n=1) - # Add OpenSBI region. soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))