From 6f6a10db5c070a6547e5c8323b5a8887d2ec0c2d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 31 Jan 2022 17:00:12 +0100
Subject: [PATCH] CHANGES: Update.

---
 CHANGES | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/CHANGES b/CHANGES
index c3d66ac4c..9272024de 100644
--- a/CHANGES
+++ b/CHANGES
@@ -21,6 +21,10 @@
 	- litex_sim:          Add .json support for --rom/ram/sdram-init.
 	- soc/add_uart:       Allow multiple UARTs in the same design.
 	- cores/cpu:          Add out-of-tree support.
+	- build/xilinx:       Add initial Yosys/NextPnr support on Artix7 (and Zynq7000 with Artix7 fabric).
+	- add_source:         Add optional copy to gateware directory.
+	- cores/jtag:         Add initial JTAG-UART/JTAGBone Altera/Intel support.
+	- LiteScope:          Add Samplerate support.
 
     [> API changes/Deprecation
 	--------------------------